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‎"Behind every stack of books there is a flood of knowledge."

FPGA Research At the University of Toronto

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University of Toronto has one of the most active FPGA research groups in the world. Comprising at least 5 faculty members and countless graduate students, we perform research in the following areas:


 

FPGA Architecture

FPGA CAD

Reconfigurable Processors

Field-Programmable Analog Arrays

Synthetic Circuit Generation (2 generations of code available!)

Automatic Circuit Design and Layout of FPGAs

Hybrid FPGA Architectures (LUT/PLA blocks)

Non-Uniform FPGA Routing Architectures

VPR: Timing-Driven Packing, Placement and Routing Tool for FPGAs (code available!)

The Transmogrifier-4 Field-Programmable System (new!)

The Transmogrifier-3 Field-Programmable System

The Transmogrifier-2 Field-Programmable System

The Transmogrifier-1 Field-Programmable System

The Transmogrifier C Hardware Description Language and Compiler

SEGA: A Detailed FPGA Router

FPGA Families

OneChip: An FPGA processor with reconfigurable logic

Graduate Theses Supervised by Jonathan Rose

  1. “Routing Algorithms and Architectures for Field-Programmable Gate Arrays,” Stephen Brown, PhD. Thesis, University of Toronto, 1992 PDF. Co-supervised by Professor Z.G. Vranesic
  2. “Technology Mapping for Lookup-Table Based Field-Programmable Gate Arrays,” Robert Francis, PhD. Thesis, University of Toronto, 1993 PDF. Co-supervised by Professor Z.G. Vranesic
  3. “Technology Mapping and Architecture of Heterogenous Field-Programmable Gate Arrays,” Jianshe He, M.A.Sc. Thesis, University of Toronto, 1993 PDF.
  4. “A Field-Programmable Systems with Reconfigurable Memory,” David Karchmer, M.A.Sc. Thesis, University of Toronto, 1994 PDF.
  5. “Architecture and Synthesis of Field-Programmable Gate Arrays with Hard-wired Connections” Kevin Chung, Ph.D. Thesis, University of Toronto, 1994 PDF.
  6. “Architecture and Algorithms for Field-Programmable Gate Arrays with Embedded Memory,” Steven J.E. Wilton, PhD thesis, University of Toronto, 1997 PDF. Co-supervised by Professor Z.G. Vranesic
  7. “Characterization and Automatic Generation of Benchmark Circuits,” Michael Hutton. Ph.D. Thesis, University of Toronto. June, 1997. PDF Co-supervised by Professor D.G. Corneil
  8. “A High-Speed Timing-Aware Router for FPGAs”, Jordan Swartz, M.A.Sc. Thesis, University of Toronto, 1998. PDF
  9. “Ultra-Fast Placement for FPGAs”, Yaska Sankar, M.A.Sc. Thesis, University of Toronto, 1999. PDF
  10. “Routing Architecture and Layout Synthesis for Multi-FPGA Systems”, Mohammed Khalid, Ph.D. Thesis, University of Toronto, 1999. PDF
  11. “Cluster-Based Architecture, Timing-Driven Packing and Timing-Driven Placement for FPGAs”, Alexander Marquardt, M.A.Sc. Thesis, University of Toronto, 1999. PDF
  12. “Real-Time Face Detection on a Configurable Hardware Platform”, Robert Mccready, M.A.Sc. Thesis, University of Toronto, 2000. PDF
  13. “The Effect of Logic Block Granularity on Deep-Submicron FPGA Performance and Density”, Elias Ahmed, M.A.Sc. Thesis, University of Toronto, 2001. PDF
  14. “Nearest Neighbour Interconnect Architecture in Deep-Submicron FPGAs”, Ajay RoopchanSingh, M.A.Sc. Thesis, University of Toronto, 2002. PDF
  15. “EVE: A CAD Tool Providing Placement and Pipelining Assistance for High-Speed FPGA Circuit Designs,” William Chow, M.A.Sc. Thesis, University of Toronto, 2001. PDF 
    Presentation in HTML 
    Presentation in Power Point
  16. “Synthetic Circuit Generation Using Clustering and Iteration,” Paul Kundarewich, M.A.Sc. Thesis, University of Toronto, 2002. PDF
  17. “Video-Rate Stereo Vision on Reconfigurable Hardware,” Ahmad Darabiha, M.A.Sc. Thesis, University of Toronto, 2003. PDF Co-supervised by Professor W.J. Maclean
  18. “Hardware Accelerated Protein Identification”, Anish Alex, M.A.Sc. Thesis, University of Toronto, 2003. PDF
  19. “A Synthesis-Oriented Omniscient Manual Editor for FPGA Circuit Design,” Tomasz Czajkowski, M.A.Sc. Thesis, University of Toronto, 2003. PDF
  20. “Automated FPGA Design, Verification and Layout,” Ian Kuon, M.A.Sc. Thesis, University of Toronto, 2004. PDF
  21. “Field-Programmable Gate Array Architectures and Algorithms Optimized for Implementing Datapath Circuits,” Andy Ye, Ph.D. Thesis, University of Toronto, 2004. PDF
  22. “Enhancing and Using an Automatic Design System for Creating FPGAs,” Aaron Egier, M.A.Sc. Thesis, University of Toronto, 2004. PDF
  23. “An FPGA-Based Hardware Development System with Multi-Gigabyte Memory Capacity And High Bandwidth,” Joshua Fender, M.A.Sc. Thesis, University of Toronto, 2005. PDF
  24. “The Microarchitecture of FPGA-Based Soft Processors,” Peter Yiannacouras, M.A.Sc. Thesis, University of Toronto, 2005. PDF Co-supervised by Professor J.G. Steffan
  25. “Improving the Area Efficiency of Heterogeneous FPGAs with Shadow Clusters,” Peter Jamieson Ph.D. Thesis, University of Toronto, 2007. PDF
  26. “Modeling Routing Demand for Early-Stage FPGA Architecture Development,” Wei Mark Fang, M.A.Sc. Thesis, University of Toronto, 2007. PDF
  27. “Portable and Scalable FPGA-Based Acceleration of a Direct Linear System Solver,” Wei Zhang, M.A.Sc. Thesis, University of Toronto, 2008. PDF . Co-supervised by Dr. V. Betz
  28. “Hardware Acceleration of a Monte Carlo Simulation for Photodynamic Therapy Treatment Planning,” William Lo, M.Sc. Thesis, University of Toronto, 2009. PDF . Co-supervised by Professor Lothar Lilge
  29. “FPGA-Based Soft Vector Processors,” Peter Yiannacouras Ph.D. Thesis, University of Toronto, 2009. PDF Co-supervised by Professor J.G. Steffan
  30. “A Hierarchical Description Language and Packing Algorithm for Heterogenous FPGAs,” Jason Luu, M.A.Sc. Thesis, University of Toronto, 2010. PDF Co-supervised by Professor J. H. Anderson
  31. “Acceleration of Coevolution Detection for Predicting Protein Interactions,” Alex Rodionov, M.A.Sc. Thesis, University of Toronto, 2011. PDF
  32. “An Energy Efficient FPGA Hardware Architecture for the Acceleration of OpenCV Object Detection,” Braiden Brousseau, M.A.Sc. Thesis, University of Toronto, 2012. PDF
  33. “On Pin-to-Wire Routing in FPGAs” Niyati Shah, M.A.Sc. Thesis, University of Toronto, 2012. PDF

 

List of Publications – Jonathan Rose

Graduate Theses 

Patents

  1. V. Betz and J. Rose, “Automatic Generation of Programmable Logic Device Architectures,” U.S. Patent # 6631510, Filed October 29, 1999, issued October 7, 2003. Google Patent Link 1 Link 2.PDF
  2. M. Khalid and J. Rose, “Multi-logic Device Systems Having Partial Crossbar and Direct Interconnection Architectures” U.S. Patent # 6604230, Filed February 9, 1999, issued August 5, 2003. Google Patent Link.
  3. V. Betz and J. Rose, “Heterogeneous interconnection architecture for programmable logic devices,” U.S. Patent # 6590419, Filed October 12, 1999, issued July 8, 2003. Google Patent Link1 Link2
  4. S. Trimberger and J. Rose, “State Saving and Restoration in Reprogrammable FPGAS,” U.S. Patent #5,844,422, filed November 13, 1996, issued Dec. 1, 1998. Google Patent Link.
  5. J. Rose and T. Bauer, “Logic BLock Structure Optimized for Sum Generation,” U.S. Patent #5,724,276, filed June 17, 1996, issued March 3, 1998. Google Patent Link.
  6. J. Rose and V. Betz, “Complementary Architectures for Field-Programmable Gate Gate Arrays,” U.S. Patent #5,537,341, filed February 10, 1995, issued July 16th, 1996 Google Patent Link.

Books

  1. I. Kuon, and J. Rose, Quantifying and Exploring the Gap Between FPGAs and ASICs , Springer, ISBN 978-1-4419-0738-7, September 2009.
  2. V. Betz, J. Rose, and A. Marquardt, Architecture and CAD for Deep-Submicron FPGAs , Springer, ISBN 0-7923-8460-1, February 1999.
  3. S. Brown, R. Francis, J. Rose, Z. Vranesic, Field-Programmable Gate Arrays , Springer/Kluwer Academic Publishers, ISBN: 978-0-7923-9248-4, May 1992.

Journal Papers

  1. W. Zhang, V. Betz and J. Rose, “Portable and Scalable FPGA-Based Acceleration of a Direct Linear System Solver”, in ACM Transactions on Reconfigurable Technology and Systemts (TRETS) Vol. 5, No. 1, March 2012, 26 pages, pp. 6-1-6-26. DOI=10.1145/2133352.2133358.
  2. P. Yiannacouras, J.G. Steffan, J. Rose, “Portable, Flexible, and Scalable Soft Vector Processors” in IEEE Transactions on VLSI, vol.20, no.8, pp.1429-1442, Aug. 2012, doi: 10.1109/TVLSI.2011.2160463.
  3. A. Rodionov, A. Bezginov, E. Tillier and J. Rose, “A New, Fast Algorithm for Detecting Protein Coevolution using Maximum Compatible Cliques,” in Algorithms for Molecular Biology, Vol. 6, No: 17, June 2011, doi:10.1186/1748-7188-6-17.
  4. J. Luu, I. Kuon, P.Jamieson, T. Campbell, A. Ye, M. Fang, K. Kent and J. Rose “VPR 5.0: FPGA CAD and Architecture Exploration Tools with Single-Driver Routing, Heterogeneity and Process Scaling,” in ACM Transactions on Reconfigurable Technology and Systems, Vol. 4., No. 4, article 32.
  5. W. Lo, K. Redmond, J. Luu, P. Chow, J. Rose, and L. Lilge, “Hardware acceleration of a Monte Carlo simulation for PDT treatment planning,” J. Biomed. Opt., Vol. 14, 014019 (2009); DOI:10.1117/1.3080134.
  6. I. Kuon, R. Tessier and J. Rose “FPGA Architecture: Survey and Challenges”, Foundations and Trends in Electronic Design Automation: Vol. 2: No 2, 2008, pp. 135-253.
  7. P. Yianancouras, J.G. Steffan and J. Rose, “Exploration and Customization of FPGA-Based Soft Processors,” in IEEE Transactions on Computer-Aided Design, Vol. 26, No. 2, February 2007, pp. 266 – 277.
  8. I. Kuon and J. Rose, “Measuring the Gap between FPGAs and ASICs” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 26, NO. 2, FEBRUARY 2007, pp. 203 – 215.
  9.  A. Ye and J. Rose “Using Bus-Based Connections to Improve Field-Programmable Gate-Array Density for Implementing Datapath Circuits” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, VOL. 14, NO. 5, May 2006, pp. 462-473.
  10.  A. Ye and J. Rose “Measuring and utilising the correlation between signal connectivity and signal positioning for FPGAs containing multi-bit building blocks” in IEE Computer & Digital Techniques Journal Vol.153, No.3,pp.146-156, May 2006.
  11.  A. Darabiha, J. Maclean and J. Rose, “Reconfigurable Hardware Implementation of a Phase-Correlation Stereo Algorithm,” in Machine Vision and Applications Journal, Vol. 17. No 2., pp. 116-132, March 2006.
  12.  Anish T. Alex, Michel Dumontier, Jonathan S. Rose, Christopher W. V. Hogue “Hardware-accelerated protein identification for mass spectrometry” Rapid Communications in Mass Spectrometry, Vol 19. No 6, March 30, 2005 PDF .
  13. P. Kundarewich and J. Rose, “Synthetic Circuit Generation Using Clustering and Iteration,” in IEEE Trans. on Computer-Aided Design, Vol 23, No. 6, June 2004, pp. 869-887. PDF.
  14. E. Ahmed and J. Rose, “The Effect of LUT and Cluster Size on Deep-Submicron FPGA Performance and Density,” in IEEE Trans. on VLSI, Vol 12, No. 3, March 2004, pp. 288-298. PDF.
  15. M. Hutton, J. Rose and D. Corneil, “Automatic Generation of Synthetic Sequential Benchmark Circuits,” in IEEE Trans. on CAD, Vol. 21, No. 8, August 2002, pp. 928-940 PDF.
  16.  S. Wilton, J. Rose, Z. Vranesic, “Structural Analysis and Generation of Synthetic Digital Circuits with Memory,” in IEEE Transactions on VLSI, Vol. 9, No. 1, February 2001, pp. 223-226 PostscriptPDF.
  17. A. Marquardt, V. Betz, and J. Rose, “Speed and Area Trade-offs in Cluster-Based FPGA Architectures,” in IEEE Transactions on VLSI, Vol. 8, No. 1, February 2000, pp. 84-93.
  18. M. Khalid and J. Rose, “A Novel and Efficient Routing Architecture for Multi- FPGA Systems,” in IEEE Transactions on VLSI, February 2000, Vol. 8, No. 1, pp. 30-39. Postscript PDF.
  19. P. Chow, S. Seo, J. Rose, K. Chung, I Rahardja, and G. Paez, “The Design of an SRAM-Based Field-Programmable Gate Array: Part I: Architecture,” in IEEE Transactions on VLSI, Vol. 7 No. 2, June 1999, pp. 191-197. Postscript PDF.
  20. P. Chow, S. Seo, J. Rose, K. Chung, I Rahardja, and G. Paez, “The Design of an SRAM-Based Field-Programmable Gate Array: Part II: Circuit Design and Layout,” in IEEE Transactions on VLSI, Vol. 7 No. 3, Sept. 1999, pp. 321-330. Postscript PDF .
  21. M. Hutton, J. Rose, J. Grossman, and D. Corneil, “Characterization and Parameterized Generation of Synthetic Combinational Benchmark Circuits,” in IEEE Trans. on CAD, Vol. 17, No. 10, October 1998, pp. 985-996. Postscript PDF.
  22.  S. Wilton, J. Rose, Z. Vranesic, “The Memory/Logic Interface in FPGAs with Large Embedded Memory Arrays,” in IEEE Trans. on VLSI. Vol. 7 No. 1, March 1999, pp. 80-91. Postscript PDF.
  23. V. Betz and J. Rose, “Effect of the Prefabricated Routing Track Distribution on FPGA Area-Efficiency,” in IEEE Transactions on VLSI, Vol. 6, No. 3, Sept. 1998, pp. 445-456. Postscript PDF.
  24. D. Lewis, D. Galloway, M. van Ierssel, J. Rose, P. Chow, “The Transmogrifier-2: A 1 Million Gate Rapid Prototyping System,” in IEEE Transactions on VLSI, Vol. 6, No. 2, June 1998, pp 188-198.Postscript PDF .
  25. V. Betz and J. Rose, “How Much Logic Should Go in an FPGA Logic Block?”, in IEEE Design & Test Magazine, Vol. 15, No. 1, Jan-March 1998, pp. 10-15. Postscript PDF .
  26. S. Brown and J. Rose, “FPGA and CPLD Architectures: A Tutorial,” in IEEE Design and Test of Computers, Vol. 12, No. 2, Summer 1996, pp. 42-57. Postscript PDF.
  27. S. Brown, J. Rose, Z. Vranesic, “A Stochastic Model to Predict The Routability of Field-Programmable Gate Arrays,” IEEE Transactions on Computer-Aided Design of Circuits and Systems, Vol. 12, No. 12, December 1993, pp. 1827-1838. Postscript PDF.
  28. J. Rose, A. El Gamal, A. Sangiovanni-Vincentelli, “Architecture of Field-Programmable Gate Arrays,” in Proceedings of the IEEE, Vol. 81, No. 7, July 1993, pp. 1013-1029.
  29. A. Sangiovanni-Vincentelli, A. El Gamal, J. Rose, “Synthesis Methods for Field-Programmable Gate Arrays,” in Proceedings of the IEEE, Vol. 81, No. 7, July 1993, pp. 1057-1083.
  30. S. Singh, J. Rose, P. Chow, D. Lewis, “The Effect of Logic Block Architecture on FPGA Performance,” IEEE JSSC, Vol. 27 No. 3, March 1992, pp. 281-287.
  31. S. Brown, J.S. Rose, Z. Vranesic, “ A Detailed Router for Field-Programmable Gate Arrays,” IEEE Transactions on Computer-Aided Design of Circuits and Systems, Vol. 11, No. 5, May 1992, pp. 620-628.
  32. J.S. Rose, S. Brown, “ Flexibility of Interconnection Structures for Field-Programmable Gate Arrays “, IEEE JSSC Vol. 26 No. 3, March 1991, pp. 277-282.
  33.  J.S. Rose, R.J. Francis, D. Lewis, and P. Chow, “Architecture of Field-Programmable Gate Arrays: The Effect of Logic Block Functionality on Area Efficiency,” IEEE JSSC, Vol. 25 No. 5, October 1990, pp. 1217-1225.
  34. J.S. Rose, “Parallel Global Routing for Standard Cells,” IEEE Transactions on Computer-Aided Design of Circuits and Systems, Vol. 9, No. 10, October 1990, pp. 1085-1095.
  35. J.S. Rose, W. Klebsch, J. Wolf, “Temperature Measurement and Equilibrium Dynamics of Simulated Annealing Placements,” IEEE Transactions on Computer-Aided Design of Circuits and Systems, Vol. 9, No. 3, March 1990, pp. 253-259.
  36. J.S. Rose, W.M. Snelgrove, Z.G. Vranesic, “Parallel Standard Cell Placement Algorithms with Quality Equivalent to Simulated Annealing,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 7, Number 3, March 1988, pp. 387-396.
  37. J.S. Rose, Z.G. Vranesic, W.M. Loucks, “FERMTOR: A Tunable Multiprocessor Architecture,” IEEE MICRO, Vol. 5, No. 4, August 1985, pp. 5-17.

Refereed Papers in Conferences

  1. B. Brousseau and J. Rose, “A Fast and Energy-Efficient Hardware Architecture for OpenCV-Compatible Object Detection,” to appear in the IEEE Conference on Field-Programmable Technology, FPT 2012, December 2012.
  2. N. Shah and J. Rose, “On the Difficulty of Pin-To-Wire Routing in FPGAs,” IEEE Conference on Field-Programmable Logic (FPL 2012), pp. 83-90, August 2012.
  3. J. Rose, J. Luu, C-W. Yu, O. Densmore, J. Goeders, A. Somerville, K.B. Kent, P. Jamieson, J. Anderson, “The VTR Project: Architecture and CAD for FPGAs from Verilog to Routing,” in ACM Symposium on FPGAs, ACM Symposium on FPGAs, February 2012, pp. 77-86.
  4. H. Wong, V. Betz and J.Rose “Comparing FPGA vs. Custom CMOS and the Impact on Processor Microarchitecture,” in FPGA ’11, ACM Symposium on FPGAs, ACM Symposium on FPGAs, February 2011, pp. 5-14.
  5. J. Luu, J. Anderson and J. Rose, “Architecture Description and Packing for Logic Blocks with Hierarchy, Modes and Complex Interconnect,” in FPGA ’11, ACM Symposium on FPGAs, ACM Symposium on FPGAs, February 2011, pp. 227-236.
  6. James Robinson, Sam Vafaee, Jonathan Scobbie, Michael Ritche and Jonathan Rosem “The Supersmall Soft Processor” in the Southern PRogrammable Logic Conference, SPL 10, March 2010.
  7. P. Yiannacouras, G. Steffan and J. Rose, “Data Parallel FPGA Workloads: Software Versus Hardware” in International Conference on Field Programmable Logic and Applications, (FPL), Prague, Czech Republic, August, 2009, pp. 51-58.
  8. W. Lo, D. Han, J. Rose, and L. Lilge, “GPU-Accelerated Monte Carlo Simulation for Photodynamic Therapy Treatment Planning,” in European Conferences on Biomedical Optics (ECBO), 2009.
  9. J. Luu, K.Redmond, W. Lo, P. Chow, L, Lilge, and J, Rose, “FPGA-based Monte Carlo Computation of Light Absorption for Photodynamic Cancer Therapy,” in IEEE Symposium on Field-programmable Custom Computing Machines (FCCM 2009). Napa Valley, California.
  10. J. Luu, I. Kuon, P.Jamieson, T. Campbell, A. Ye, M. Fang, and J. Rose “VPR 5.0: FPGA CAD and Architecture Exploration Tools with Single-Driver Routing, Heterogeneity and Process Scaling,” in FPGA ’09, ACM Symposium on FPGAs, ACM Symposium on FPGAs, February 2009, pp. 133-142.
  11. W. Zhang, V. Betz and J. Rose, “Portable and Scalable FPGA-Based Acceleration of a Direct Linear System Solver,” in IEEE Int’l Conference on Field-Programmable Technology, FPT ’08, December 2008, pp. 17-24.
  12. P. Yiannacouras, J. Rose, and J. G. Steffan, “VESPA: Portable, Scalable, and Flexible FPGA-BasedVector Processors,” in Int’l Conf on Compilers, Architecture and Synthesis for Embedded Systems (CASES 2008), September 2008, pp. 61-70.
  13. I. Kuon and J. Rose, “Automated Transistor Sizing for FPGA Architecture Exploration” in DAC ’08, ACM/IEEE Design Automation Conference, June 2008, pp. 792-795.
  14. W-M. Fang and J. Rose “Modeling Routing Demand in Early-Stage FPGA Architecture Development,” in ACM Symposium on FPGAs, February 2008, pp. 139-148.
  15. I. Kuon and J. Rose “Area and Delay Trade-offs in the Circuit and ArchitectureDesign of FPGAs,” in ACM Symposium on FPGAs, February 2008, pp. 149-158.
  16. P. Jamieson and J. Rose, “Architecting Hard Crossbars on FPGAs and Increasing their Area-Efficiency with Shadow Clusters,” in IEEE International Conference on Field Programmable Technology (FPT07), 2007, Kitakyushu, Japan, Decemeber 2007, pp. 57-64.
  17. P. Jamieson and J. Rose, “Enhancing the Area-Efficiency of FPGAs with Hard Circuits Using Shadow Clusters,” in IEEE International Conference on Field Programmable Technology (FPT06), 2006, Bangkok, Thailand, Decemeber 2006, pp. 1-8.
  18. I. Kuon and J. Rose, “Measuring the Gap between FPGAs and ASICs,” ACM Symposium on FPGAs, February 2006, pp. 21-30.
  19. P. Yiannacouras, J. G. Steffan and J. Rose, “Application Specific Customization of Soft Processor Microarchitecture” ACM Symposium on FPGAs, February 2006, pp. 201-210.
  20. P. Yiannacouras, J. Rose, and J. G. Steffan, “The Microarchitecture of FPGA-Based Soft Processors,” International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES 2005), September 2005, San Francisco, CA, pp. 202-212.
  21. P. Jamieson and J. Rose, “A Verilog RTL Synthesis Tool For Heterogeneous FPGAs,” in 2005 Int’l Conference on Field Programmable Logic and Applications (FPL’05), Tampere, Finland, August 2005, pp. 305-310.
  22. A. Ye and J. Rose, “Measuring and Utilizing the Correlation Between Signal Connectivity and Signal Positioning for FPGAs Containing Multi-Bit Building Blocks,” in 2005 Int’l Conf. on Field Programmable Logic and Applications (FPL’05), Tampere, Finland, August 2005, pp 159-166.
  23. P. Jamieson and J. Rose, “Mapping Multiplexers onto Hard Multipliers in FPGAs,” in the 3rd International IEEE Northeast Workshop on Circuits & Systems.
  24. I. Kuon, A. Egier and J. Rose, “Design, Layout and Verification of an FPGA using Automated Tools” in FPGA ’05, ACM Symposium on FPGAs, February 2005, pp 215-226. PDF
  25. A.G. Ye, and J. Rose, “Using Bus-Based Connections to Improve Field-Programmable Gate Array Density for Implementing Datapath Circuits” in FPGA ’05, ACM Symposium on FPGAs, February 2005, pp 3-13. PDF
  26. David Lewis, Elias Ahmed, Gregg Baeckler, Vaughn Betz, Mark Bourgeault, David Cashman, David Galloway, Mike Hutton, Chris Lane, Andy Lee, Paul Leventis, Sandy Marquardt, Cameron McClintock, Ketan Padalia, Bruce Pedersen, Giles Powell, Boris Ratchev, Srinivas Reddy, Jay Schleicher, Kevin Stevens, Richard Yuan, Richard Cliff and Jonathan Rose, “The Stratix II Logic and Routing Architecture” in FPGA ’05, ACM Symposium on FPGAs, February 2005, pp 14-20. PDF
  27. A. Ye and J. Rose, “Using Multi-Bit Logic Blocks and Automated Packing to Improve Field-Programmable Gate Array Density for Implementing Datapath Circuits,” in 2004 International Conference on Field Programmable Technology (FPT ’04), December 2004, pp. 129-136. PDF
  28.  A. Alex, J, Rose, R, Isserlin-Weinberger, C. Hogue, “Hardware Accelerated Novel Protein Identification,” in Int’l Symp. on Field-Programmable Logic, Aug 2004, pp. 13-22. PDF .
  29. T. Czajkowski and J. Rose, “A Synthesis-Oriented Omniscient Manual Editor, ” in FPGA ’04, ACM Symposium on FPGAs, February 2004, pp 89-98. PDF
  30.  J. Rose, “Hard vs. Soft: The Central Question of Pre-Fabricated Silicon,” 34th International Symposium on Multiple-Valued Logic (ISMVL’04), May 2004, pp. 2-5 PDF .
  31.  J. Fender and J. Rose, “A High-Speed Ray Tracing Engine Built on a Field-Programmable System,” in IEEE International Conf. On Field-Programmable Technology, December 2003, pp. 188-195.PDF .
  32.  P. Yiannacouras and J. Rose, “A Parameterized Automatic Cache Generator for FPGAs,” in IEEE Int’l Conf. On Field-Programmable Technology, Dec. 2003, pp. 324-327. PDF .
  33.  A. Ye, J. Rose and D. Lewis, “Architecture of Datapath-Oriented Coarse-Grain Logic and Routing for FPGAs,” in IEEE CICC 2003, San Jose, CA, September 2003, pp. 61-64. PDF .
  34.  A. Darabiha, J. Rose and W. J. MacLean “Video-Rate Stereo Depth Measurement on Programmable Hardware” Proceedings of the 2003 IEEE Computer Society Conference on Computer Vision & Pattern Recognition, June 1622, Madison, WI, Vol. 1, pp. 203-210. PDF Slides .
  35.  D. Lewis, V. Betz, D. Jefferson, A. Lee, C. Lane, P. Leventis, S. Marquardt, C. McClintock, B. Pedersen, G. Powell, S. Reddy, C. Wysocki, R. Cliff, and J. Rose, “The Stratix Routing and Logic Architecture” in FPGA ’03, ACM. Symp. FPGAs, February 2003, pp. 15-20. PDF .
  36.  K. Padalia, R. Fung, M. Bourgeault, A. Egier and J. Rose, “Automatic Transistor and Physical Design of FPGA Tiles From An Architectural Specification” in FPGA 2003, ACM Symp. FPGAs, Feburary 2003, pp. 164-172. PDF .
  37.  A. Ye, J. Rose, D. Lewis “Synthesizing Datapath Circuits for FPGAs with Emphasis on Area Minimization”, Proceedings of 2002 IEEE International Conference on Field-Programmable Technology”, Hong Kong, December 2002, pp. 219-227 PDF .
  38.  A. Roopchansingh and J. Rose, “Nearest Neighbour Interconnect Architecture in Deep Submicron FPGAs,” IEEE Custom Integrated Circuits Conference, San Diego, CA, May 2002, pp. 59 – 62.PDF
  39. W. Chow and J. Rose, “EVE: A CAD Tool for Manual Placement and Pipelining Assistance of FPGA Circuits,” in FPGA 2002, ACM Symp. FPGAs, Feburary 2002, pp. 85-94. PDF
  40.  M. Sheng and J. Rose, “Mixing Buffers and Pass Transistors in FPGA Routing Architectures,” in FPGA 2001, ACM Symp. FPGAs, Feburary 2001, pp. 75-84. Postscript PDF
  41.  E. Ahmed and J. Rose, “The Effect of LUT and Cluster Size on Deep-Submicron FPGA Performance and Density,” in FPGA 2000, ACM Symp. FPGAs, February 2000, pp. 3-12. Postscript PDF
  42. V. Betz and J. Rose, “Automated Generation of FPGA Architectures,” in FPGA 2000, ACM Symp. on FPGAs, February 2000, pp. 175-186 Postscript PDF .
  43. A. Marquardt, V. Betz, and J. Rose, “Timing-Driven Placement for FPGAs,” in FPGA 2000, ACM Symp. on FPGAs, February 2000, pp. 203-213 Postscript PDF .
  44.  V. Betz and J. Rose, “Circuit Design, Transistor Sizing and Wire Layout of FPGA Interconnect,” IEEE Custom Integrated Circuits Conference, San Diego, CA, May 1999, pp. 171 – 174.Postscript PDF
  45. V. Betz and J. Rose, “FPGA Routing Architecture: Segmentation and Buffering to Optimize Speed and Density,” in FPGA `99, ACM Symp. on FPGAs, pp. 59-68. FPGA `99, ACM Symp. on FPGAs, Feb 1999, pp. 140-149. Postscript PDF.
  46. A. Marquardt, V. Betz, and J. Rose, “Using Cluster-Based Logic Blocks and Timing-Driven Packing to Improve FPGA Speed and Density,” in FPGA `99, ACM Symp. on FPGAs, pp.37-46.Postscript PDF.
  47. Y. Sankar and J. Rose,”Trading Quality for Compile Time: Ultra-Fast Placement for FPGAs” in FPGA `99, ACM Symp. on FPGAs, pp. 157-166. Postscript PDF
  48. J. Swartz, V. Betz and J. Rose, “A Fast Routability-Driven Router for FPGAs” in FPGA `98, ACM Symp. on FPGAs, Feb 1998, pp. 140-149. Postscript PDF.
  49. M. Khalid and J. Rose, “A Hybrid Complete-Graph Partial-Crossbar Routing Architecture for Multi-FPGA Systems,” in FPGA `98, ACM Symp. on FPGAs, Feb 1998, pp. 45-54. Postscript PDF.
  50. V. Betz and J. Rose, “Cluster-Based Logic Blocks for FPGAs: Area-Efficiency vs. Input Sharing and Size,” in IEEE CICC 1997, Santa Clara, CA, pp. 551-554. Postscript PDF.
  51. J. Rose and D. Hill, “Architectural and Physical Design Challenges for One-Million Gate FPGAs and Beyond,” in FPGA `97, ACM Symp. on FPGAs, Feb 1997, pp. 129-132 (invited) PostscriptPDF.
  52.  M. Hutton, J. Rose, D. Corneil, “Generation of Synthetic Sequential Benchmark Circuits,” in FPGA `97, ACM Symp. on FPGAs, Feb 1997, pp. 149-155. Postscript PDF.
  53.  S. Wilton, J. Rose, Z. Vranesic, “Memory-to-Memory Connection Structures in FPGAs with Embedded Memory Arrays,” in FPGA `97, ACM Symp. on FPGAs, Feb 1997, pp. 10-16. PostscriptPDF.
  54. D. Lewis, D. Galloway, M. van Ierssel, J. Rose, P. Chow, “The Transmogrifier-2: A 1 Million Gate Rapid Prototyping System,” in FPGA `97, ACM Symp. on FPGAs, Feb 1997, pp. 53-61.Postscript PDF.
  55. V. Betz and J. Rose, “Directional Bias and Non-Uniformity in FPGA Global Routing Architectures,” in ICCAD 1996, pp. 652-659, November 1996. FPGA ’95, pp. 10-16. Postscript PDF.
  56. M. Hutton, J.P. Grossman, J. Rose, D. Corneil, “Characterization and Parameterized Random Generation of Digital Circuits,” in the 1996 Design Automation Conference, June, 1996, pp. 94-99.Postscript PDF.
  57.  S. Wilton, J. Rose, Z. Vranesic, ” Memory/Logic Interconnect Flexibility in FPGAs with Large Embedded Memory Arrays ,” in CICC 96, the IEEE Custom Integrated Circuits Conf., San Deigo, CA, May 1996, pp. 144-147. Postscript PDF.
  58.  T. Ngai, J. Rose, S. Wilton, “ An SRAM-Programmable Field-Configurable Memory ,” in CICC 95, the IEEE Custom Integrated Circuits Conf., Santa Clara, CA, May 1995, pp. 499-502.Postscript PDF.
  59. V. Betz, J. Rose, “Improving FPGA Performance via the Use of Architecture Families,” 3rd ACM Intl Symposium on Field-Programmable Gate Arrays, FPGA ’95, pp. 10-16. Postscript PDF.
  60.  S. Wilton, J. Rose, Z. Vranesic, “ Architecture of Centralized Field-Configurable Memory ,” 3rd ACM Intl Symposium on Field-Programmable Gate Arrays, FPGA 95, pp. 97-103. Postscript PDF.
  61. D. Karchmer, J. Rose, “Definition and Solution of The Memory Packing Problem for Field-Programmable Systems,” in the ACM/IEEE International Conference on Computer-Aided Design, ICCAD 94, pp. 20-26.
  62. J. He, J. Rose, “Advantages of Heterogeneous Logic Block Architectures for FPGAs,” IEEE Custom Integrated Circuits Conf. 1993, (CICC 93), San Diego, May 1993 pp. 7.4.1 – 7.4.5. PostscriptPDF
  63. P. Chow, S. Seo, K. Chung, G. Paez, J. Rose, “A High-Speed FPGA Using Programmable Mini-Tiles,” in Symposium on Integrated Systems (formerly Conference on Advanced Research in VLSI), Washington, 1993, pp. 104-122.
  64. B. Fallah, J. Rose, “Timing-Driven Routing Segment Assignment in FPGAs,” in the Canadian Conference on VLSI, CCVLSI 92, October 1992, pp. 124-130.
  65. B. Tseng, J. Rose, S. Brown, “Using Architectural and CAD Interactions to Improve FPGA Routing Architectures,” in the IEEE, ICCD 92 October 1992, pp. 99 – 104. Postscript PDF
  66. K. Chung, J. Rose, “TEMPT: Technology Mapping for the Exploration of FPGA Architectures with Hard-Wired Connections,” Proc. 29th ACM/IEEE Design Automation Conference, June 1992, Anaheim, CA, pp. 361-367.
  67. R.J Francis, J. Rose, Z. Vranesic, “Technology Mapping Lookup Table-Based FPGAs for Performance” Proc. 1991 IEEE International Conference on Computer-Aided Design (ICCAD), November 1991, pp. 568-571.
  68. R.J Francis, J. Rose, Z. Vranesic, “Chortle-crf: Fast Technology Mapping for Lookup Table-Based FPGAs,” 28th ACM/IEEE Design Automation Conference, June 1991, pp. 227-233.
  69. S. Singh, J. Rose, D. Lewis, K. Chung, P. Chow “Optimization of Field-Programmable Gate Array Logic Block Architecture for Speed,” in IEEE Custom Integrated Circuits Conference 91, CICC, May 1990, pp. 6.1.1 – 6.1.6.
  70. S. Brown, J.S. Rose, Z. Vranesic, “A Detailed Router for Field Programmable Gate Arrays” Proc. 1990 IEEE International Conference on Computer-Aided Design (ICCAD), pp. 382-385, November 1990. Designated as a distinguished paper.
  71. R.J Francis, J. Rose, K. Chung, “Chortle: A Technology Mapping Program for Lookup Table-Based Field Programmable Gate Arrays,” Proc. 27th ACM/IEEE Design Automation Conference, June 1990, pp. 613-619.
  72.  J. Rose, S. Brown, “The Effect of Switch Box Flexibility on Routability of Field Programmable Gate Arrays,” IEEE Proc. Custom Integrated Circuits Conference, (CICC), Boston May 1990, pp. 27.5.1 – 27.5.4.
  73. J.S. Rose, R.J. Francis, P. Chow, and D. Lewis, “The Effect of Logic Block Complexity on Area of Programmable Gate Arrays,” Proc. IEEE Custom Integrated Circuits Conference, (CICC), San Diego, May 1989, pp. 5.3.1 – 5.3.5. Postscript PDF.
  74. J.S. Rose, W. Klebsch, J. Wolf, “Temperature Measurement of Simulated Annealing Placements,” in IEEE International Conference on Computer-Aided Design, (ICCAD), November 1988, pp. 514-517.
  75. J.S. Rose, “The Parallel Decomposition and Implementation of an Integrated Circuit Global Router,” ACM Sigplan Symposium on Parallel Programming: Experience with Applications, Languages and Systems, July 1988, pp. 138-145.
  76. J.S. Rose, “LocusRoute: A Parallel Global Router for Standard Cells,” Proc. 25th Design Automation Conference, June 1988, pp. 189-195.
  77. J.S. Rose, D.R. Blythe, W. Snelgrove, Z. Vranesic, “Fast, High Quality VLSI Placement on an MIMD Multiprocessor,” Proc. ICCAD 86, Nov. 1986, pp. 42-45.
  78. Z.G. Vranesic, J.S. Rose, W.M. Loucks, “A Flexible Architecture MIMD Supercomputer for Non-Numeric Applications,” First International Conference on Supercomputing Systems, December 1985, pp. 455-459.
  79. J.S. Rose, W.M. Snelgrove, Z.G. Vranesic, “ALTOR: An Automatic Standard Cell Layout Program,” 1985 Canadian Conference on Very Large Scale Integration, November 1985, pp. 169-173. This paper won a best paper award.

Refereed Presentations at Workshops

  1. M. Khalid and J. Rose, “Experimental Evaluation of Mesh and Partial Crossbar Routing Architectures for Multi-FPGA Systems,” in IFIP IWLAS `97, Int’l Workshop on Logic and Architecture Synthesis, Grenoble, France, December 1997, pp. 119-127. Postscript PDF
  2. V. Betz and J. Rose, “VPR: A New Packing, Placement and Routing Tool for FPGA Research,” in 7th International Workshop on Field-Programmable Logic, London, August 1997, pp. 213-222.Postscript PDF.
  3. M. Khalid and J. Rose, “The Effect of Fixed I/O Pin Positioning on The Routability and Speed of FPGAs,” Proc. Canadian Workshop of Field-Programmable Devices, FPD 95, pp. 94-102. PostscriptPDF.
  4. D. Galloway, D. Karchmer, P. Chow, D. Lewis, J. Rose, “The Transmogrifier: The University of Toronto Field-Programmable System,” in the 1994 Canadian Workshop on Field-Programmable Devices. (formerly the CMC VLSI Workshop).
  5. J. He, J. Rose, “Technology Mapping for Heterogeneous FPGAs,” in the ACM International Workshop on Field-Programmable Gate Arrays 1994, February 1994, FPGA ’94. Postscript PDF.
  6. K. Chung, S. Singh, J. Rose, P. Chow, “Using Hierarchical Logic Blocks to Improve the Speed of Field-Programmable Gate Arrays,” International Workshop on Field Programmable Logic and Applications, Sept 1991, Oxford, UK.
  7. P. Chow, S.O. Seo, D. Au, B. Fallah, C. Li, J.Rose, “A 1.2um CMOS FPGA Using Cascaded Logic Blocks and Segmented Routing,” International Workshop on Field Programmable Logic and Applications, Sept 1991, Oxford, UK.
  8. J-M. Vuillamy, Z. Vranesic, J.Rose, “Performance Evaluation and Enhancement of FPGAs,” International Workshop on Field Programmable Logic and Applications, Sept 1991, Oxford, UK.

Source:

http://www.eecg.toronto.edu/EECG/RESEARCH/FPGA.html

http://www.eecg.toronto.edu/~jayar/pubs/pubs.html#CICC93He

http://www.eecg.toronto.edu/~jayar/pubs/theses/theses.html

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