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IP cores for the Altera DE2 board

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Here you can download the IP cores designed to be used in your hardware designs on the DE2 board. These cores were create to simplify the designs that wish to use the hardware natively (i.e., not through the Avalon bus).

Table 1. Available cores

Core Description PDF Download Core
PS/2 Controller Provides a simple interface to the PS/2 keyboards and mice. PDF ZIP
Audio Controller Provides an interface to the audio codec on the DE2 board. PDF ZIP
Video-in Controller Provides a simple interface to the video decoder on the DE2 board. PDF ZIP
Audio and video-in configuration module Performs the configuration necessary for the audio and video chips. PDF ZIP
Voice Recorder Demo Demonstration of the DE2 board capabilities. PDF ZIP

[DIR] Parent Directory 27-Aug-2013 15:04 – [DIR] 08projectvids/ 04-Mar-2012 14:30 – [DIR] AudioVideoCores/ 02-Sep-2008 13:13 – [   ] FirstHandout.pdf 21-Aug-2008 14:24 38k [   ] Lab2_starterkit.zip 28-Aug-2008 15:51 5k [   ] Lab3_starterkit.zip 21-Sep-2008 15:44 8k [   ] Lab4_starterkit.zip 30-Sep-2008 14:26 14k [   ] Lab5_starterkit.zip 14-Oct-2008 09:45 11k [   ] Lab6_starterkit.zip 20-Oct-2008 19:58 152k [   ] Lab7_starterkit.zip 20-Oct-2008 20:08 256k [   ] Logic_Scope_Tutorial..> 27-Sep-2008 15:01 4.1M [   ] PlavecProjectAdvice.pdf 05-Nov-2008 09:19 47k [TXT] PracticeProblemsForE..> 23-Nov-2008 12:00 5k [TXT] PracticeProblemsForM..> 15-Sep-2008 12:03 4k [DIR] PrevExams/ 23-Nov-2008 11:42 – [   ] PublishedProject08.pdf 26-Oct-2008 20:15 846k [TXT] lab1.htm 21-Aug-2008 15:33 127k [   ] lab1.pdf 07-Sep-2008 12:08 44k [DIR] lab1_files/ 21-Aug-2008 15:33 – [   ] lab2.pdf 16-Sep-2008 17:39 139k [   ] lab3.pdf 26-Sep-2008 13:49 77k [   ] lab4.pdf 27-Sep-2008 15:48 171k [   ] lab5.pdf 13-Oct-2008 20:10 110k [   ] lab6.pdf 23-Oct-2008 16:18 311k [   ] lab7.pdf 20-Oct-2008 20:06 69k [TXT] labs.htm 27-Oct-2008 11:12 11k [   ] midterm08soln.pdf 19-Oct-2008 12:13 305k [DIR] oldmidterms/ 05-Oct-2008 14:42 – [TXT] project.htm 18-Aug-2008 16:53 9k [TXT] sched08.htm 19-Nov-2008 09:25 10k [DIR] sched08_files/ 21-Aug-2008 14:48 – [DIR] vga/ 26-Nov-2008 22:00 – [DIR] videos/ 26-Oct-2008 20:12 – [DIR] videoselection/ 03-Dec-2008 09:16 –

Graduate Theses Supervised by Jonathan Rose

  1. “Routing Algorithms and Architectures for Field-Programmable Gate Arrays,” Stephen Brown, PhD. Thesis, University of Toronto, 1992 PDF. Co-supervised by Professor Z.G. Vranesic
  2. “Technology Mapping for Lookup-Table Based Field-Programmable Gate Arrays,” Robert Francis, PhD. Thesis, University of Toronto, 1993 PDF. Co-supervised by Professor Z.G. Vranesic
  3. “Technology Mapping and Architecture of Heterogenous Field-Programmable Gate Arrays,” Jianshe He, M.A.Sc. Thesis, University of Toronto, 1993 PDF.
  4. “A Field-Programmable Systems with Reconfigurable Memory,” David Karchmer, M.A.Sc. Thesis, University of Toronto, 1994 PDF.
  5. “Architecture and Synthesis of Field-Programmable Gate Arrays with Hard-wired Connections” Kevin Chung, Ph.D. Thesis, University of Toronto, 1994 PDF.
  6. “Architecture and Algorithms for Field-Programmable Gate Arrays with Embedded Memory,” Steven J.E. Wilton, PhD thesis, University of Toronto, 1997 PDF. Co-supervised by Professor Z.G. Vranesic
  7. “Characterization and Automatic Generation of Benchmark Circuits,” Michael Hutton. Ph.D. Thesis, University of Toronto. June, 1997. PDF Co-supervised by Professor D.G. Corneil
  8. “A High-Speed Timing-Aware Router for FPGAs”, Jordan Swartz, M.A.Sc. Thesis, University of Toronto, 1998. PDF
  9. “Ultra-Fast Placement for FPGAs”, Yaska Sankar, M.A.Sc. Thesis, University of Toronto, 1999. PDF
  10. “Routing Architecture and Layout Synthesis for Multi-FPGA Systems”, Mohammed Khalid, Ph.D. Thesis, University of Toronto, 1999. PDF
  11. “Cluster-Based Architecture, Timing-Driven Packing and Timing-Driven Placement for FPGAs”, Alexander Marquardt, M.A.Sc. Thesis, University of Toronto, 1999. PDF
  12. “Real-Time Face Detection on a Configurable Hardware Platform”, Robert Mccready, M.A.Sc. Thesis, University of Toronto, 2000. PDF
  13. “The Effect of Logic Block Granularity on Deep-Submicron FPGA Performance and Density”, Elias Ahmed, M.A.Sc. Thesis, University of Toronto, 2001. PDF
  14. “Nearest Neighbour Interconnect Architecture in Deep-Submicron FPGAs”, Ajay RoopchanSingh, M.A.Sc. Thesis, University of Toronto, 2002. PDF
  15. “EVE: A CAD Tool Providing Placement and Pipelining Assistance for High-Speed FPGA Circuit Designs,” William Chow, M.A.Sc. Thesis, University of Toronto, 2001. PDF 
    Presentation in HTML 
    Presentation in Power Point
  16. “Synthetic Circuit Generation Using Clustering and Iteration,” Paul Kundarewich, M.A.Sc. Thesis, University of Toronto, 2002. PDF
  17. “Video-Rate Stereo Vision on Reconfigurable Hardware,” Ahmad Darabiha, M.A.Sc. Thesis, University of Toronto, 2003. PDF Co-supervised by Professor W.J. Maclean
  18. “Hardware Accelerated Protein Identification”, Anish Alex, M.A.Sc. Thesis, University of Toronto, 2003. PDF
  19. “A Synthesis-Oriented Omniscient Manual Editor for FPGA Circuit Design,” Tomasz Czajkowski, M.A.Sc. Thesis, University of Toronto, 2003. PDF
  20. “Automated FPGA Design, Verification and Layout,” Ian Kuon, M.A.Sc. Thesis, University of Toronto, 2004. PDF
  21. “Field-Programmable Gate Array Architectures and Algorithms Optimized for Implementing Datapath Circuits,” Andy Ye, Ph.D. Thesis, University of Toronto, 2004. PDF
  22. “Enhancing and Using an Automatic Design System for Creating FPGAs,” Aaron Egier, M.A.Sc. Thesis, University of Toronto, 2004. PDF
  23. “An FPGA-Based Hardware Development System with Multi-Gigabyte Memory Capacity And High Bandwidth,” Joshua Fender, M.A.Sc. Thesis, University of Toronto, 2005. PDF
  24. “The Microarchitecture of FPGA-Based Soft Processors,” Peter Yiannacouras, M.A.Sc. Thesis, University of Toronto, 2005. PDF Co-supervised by Professor J.G. Steffan
  25. “Improving the Area Efficiency of Heterogeneous FPGAs with Shadow Clusters,” Peter Jamieson Ph.D. Thesis, University of Toronto, 2007. PDF
  26. “Modeling Routing Demand for Early-Stage FPGA Architecture Development,” Wei Mark Fang, M.A.Sc. Thesis, University of Toronto, 2007. PDF
  27. “Portable and Scalable FPGA-Based Acceleration of a Direct Linear System Solver,” Wei Zhang, M.A.Sc. Thesis, University of Toronto, 2008. PDF . Co-supervised by Dr. V. Betz
  28. “Hardware Acceleration of a Monte Carlo Simulation for Photodynamic Therapy Treatment Planning,” William Lo, M.Sc. Thesis, University of Toronto, 2009. PDF . Co-supervised by Professor Lothar Lilge
  29. “FPGA-Based Soft Vector Processors,” Peter Yiannacouras Ph.D. Thesis, University of Toronto, 2009. PDF Co-supervised by Professor J.G. Steffan
  30. “A Hierarchical Description Language and Packing Algorithm for Heterogenous FPGAs,” Jason Luu, M.A.Sc. Thesis, University of Toronto, 2010. PDF Co-supervised by Professor J. H. Anderson
  31. “Acceleration of Coevolution Detection for Predicting Protein Interactions,” Alex Rodionov, M.A.Sc. Thesis, University of Toronto, 2011. PDF
  32. “An Energy Efficient FPGA Hardware Architecture for the Acceleration of OpenCV Object Detection,” Braiden Brousseau, M.A.Sc. Thesis, University of Toronto, 2012. PDF
  33. “On Pin-to-Wire Routing in FPGAs” Niyati Shah, M.A.Sc. Thesis, University of Toronto, 2012. PDF

 

2006

Last First Advisor Month Title pdf
Saldana Manuel Chow September A Parallel Programming Model for a Multi-FPGA Multiprocessor Machine pdf
Ta-Min Richard Lie September Splitting Interfaces: Making Trust Between Applications and Operating Systems Configurable pdf
Tam Adrian Stumm September QDO: A QUIESCENT STATE CALLBACK FACILITY pdf
Da Silva Jeffrey Steffan March A Probabilistic Pointer Analysis for Speculative Optimizations pdf
Labrecque Martin Steffan January Towards a Compilation Infrastructure for Network Processors pdf
Gao Dapeng Jacobsen May Aspect-Oriented Middleware pdf
Raman Madhusudan Voss September Trace-Based Optimization for Precomputation and Prefetching pdf
Worby Joshua MacLean December Multi-Resolution Graph Cuts for Stereo-Motion Estimation pdf

Jonathan Rose

[Jonathan Rose]

Professor in The Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto


 Graduate Course January 2014: Creative Applications for Mobile Devices


 University of Toronto FPGA Seminar


Contact Information
Biography
Research
Publications
Graduate Theses
University of Toronto FPGA CAD Software – New! VTR 1.0 Full Release Project including VPR 6.0 Timing Driven
Current Graduate Students
Former Graduate Students
Research on FPGAs at the University of Toronto
Research Support Acknowledgement
HDL Circuit Benchmarks Designed at UofT

 Computer Group  The Edward S. Rogers Sr. Department of Electrical & Computer Engineering 
 Faculty of Applied Science & Engineering  University of Toronto 

 

Source:

http://www.eecg.toronto.edu/~jayar/ece241_08F/

http://www.eecg.toronto.edu/~jayar/ece241_08F/AudioVideoCores/

http://www.eecg.toronto.edu/~jayar/

http://www.eecg.toronto.edu/~jayar/pubs/theses/theses.html

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This entry was posted on September 21, 2013 by in Electronic & Computer Engineering, IC Design & Fabrication, Science & Technology.
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