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Standard Cell Development Tutorial


This tutorial will walk through the steps taken when creating your own customized standard cell library. Similar steps will be taken when preparing a custom block (i.e., SRAM) for inclusion in an Encounter generated layout. You may want to revisit the Schematic Entry and Layout Entry tutorials before doing this new tutorial

The following Cadence CAD tools will be used in this tutorial:

  • Virtuoso Schematic Composer for schematic capture.
  • Virtuoso Layout Editing for layout.
  • SignalStorm for Library Timing Characterization.
  • Abstract Generator for LEF Generation.

Directory Setup

Please create a directory for the design (e.g. tutorial, should have it), link any necessary library files to your directory such that it will be easier to navigate to them, another for the SignalStorm files (e.g. signalstorm), and finally one for the Abstract Generator files (e.g. myabstract):

cd tutorial
mkdir signalstorm
mkdir myabstract

In your signalstorm folder, save the following file that you will need later for characterizing the timing of the standard cells we create:

Draw Standard Cells in Cadence

For this tutorial we’ll only create two standard cells, a unit sized inverter (INVX1) and an inverter double the size of the unit (INVX2). This is done by first running icfb from the tutorial folder and creating a new library that you will use for your standard cells. One suggested name for the library is your Poly user name followed by _stdcells. For example, I named my library ‘grose_stdcells’ since grose is my user name. Attach your library to the TSMC 0.20um technology file. You might want to refer to the Cadence custom design tutorials for a reminder. Now create your two cells, INVX1 and INVX2, including schematic, layout, symbol, and extracted view. Be sure you include pins (A, Y, gnd!, vdd!) in the layout where necessary and run DRC, LVS, extract each, and simulate as you go. The completed cells should look like the following:



There are a few things about the above two cells that you should make note of. First, the unit (X1) sized gate has an NMOS width of 500nm and PMOS width of 1um while X2 has NMOS of 1um and PMOS of 2um. Second, you must draw the layout with a lot of space in between the pull up and pull down networks to allow for routing — this is referred to as the routing grid. For these two inverter cells, I’ve chosen to use the same routing grid as the OSU standard cells. In fact, the only real difference between these cells and the OSU cells is that my unit (X1) is smaller. You should read about the routing grid at before completing the standard cells. The routing grid for the OSU standard cell library (and yours):

Create Standard Cell Netlist

Now we are going to create a single schematic that contains symbols for each standard cell you have created (INVX1 and INVX2 in this particular case). This schematic is used to create a single netlist including all standard cells in your library so that you can more easily create the LEF file that describes everything you need. Start by creating a new library, I’m calling mine grose_signalstorm, and place instances of all cells in a new schematic cell (ss_cells for me) but do not wire anything.

Remember the point of this all inclusive schematic is to create a netlist that will be used by SignalStorm for characterizing your library (i.e., timing simulations). Before proceeding, you may want to walk through the prior steps taken when creating your cells. In particular, make sure you placed pins in the layout for vdd!, gnd!, A, and Y. You will also need an extracted view for each cell but let’s make sure to include parasitics when doing the extract as this will lead to more accurate timing information (this is what we’re after here). After you are confident about the design of each cell in your library, return to your newly created schematic cell and open Analog Environment by selecting Tools -> Analog Environment. When the Analog Environment window pops up go to Setup -> Environment… and type ‘extracted’ at the front of Switch View List.

Click Apply then OK and we will now create the netlist. There is no need to setup stimuli or model files, we are only creating the netlist. In fact, go to Setup -> Model Libraries… and delete any libraries that are listed. To do this, select Simulation -> Netlist -> Create and you should see a window pop up displaying the netlist itself. In this new window, select File -> Save As… and save the file in the signalstorm directory created earlier and give it a name such as grose_stdcells.scs (you would replace grose with your user name). Before closing anything, it is a good idea to check that the file has been saved correctly in the signalstorm folder.

Setup Files for SignalStorm

After you have created the netlist for your standard cell library, you should cd to the signalstorm folder. Here you should see four files:,, ss_script and user_stdcells.scs (user is your user name).

The netlist created from Spectre also needs to be tweaked a bit. Open the netlist by issuing the command gedit grose_stdcells.scs (your equivalent) at the command prompt. With the netlist open, search and replace all instances of “vdd!” with “vdd”. We need to also replace all instances of net 0 with “gnd”. Perform three different replacements: Replace ” 0 ” with ” gnd “, then “(0 ” with “(gnd ” and finally ” 0)” with ” gnd)”.

Next, you need to append ” vdd gnd” to the port lists of each of your subcircuits (lines that starts with subckt) but you will need to do this manually.

Save your netlist and exit gedit.

Running SignalStorm

For this tutorial you will need a few extra files, all the results of the previous tutorials, make sure you have those.

From the encounter directory type:


The command encounter (no &) starts SOC Encounter in the foreground and you should get the encounter startup window:

The window has three main areas:

  • Menu Bar (top)
  • Select Bar (right)
  • Display Area (middle)

Please try to familiarize yourself with the main window, click on the menus, on the Toolbar widgets, etc. For more information on the various Cadence tools I encourage you to read the corresponding manuals. You can get to the menu reference manual for Encounter by pressing Help on the right of the Menu Bar. You can also directly access documents at /opt/cadence/SOC62/doc/encounter. For those that want to learn Encounter into more depth there are some really nice tutorials in /opt/cadence/SOC62/share/fe/gift/tutorials/dtmf/work_fe. Spend some time browsing the manuals to understand what is available (a lot!). During the semester you will have to look for information in the on-line manuals to complement the (limited) info provided in these tutorials. You can think of this tutorial as a tiny subset of the one available under help.

Now we can start using Encounter. First we need to import the synthesized netlist (the result of RTL synthesis with RTL Compiler). Click on Design -> Import Design… and the Design Import window should pop-up (as an aside, it seems you can also import RTL directly, I assume this means you can do RTL synthesis in Encounter directly without using RC, it would be interesting to try this and see how it works). Now you need to fill in the Verilog netlist (use the browser button on the right to navigate to your synthesized netlist, in my case accu_synth.v in ../synthesis, make sure you click on Add, then on Close

Then click on Auto Assign for the Top Cell assignment. Then we need to specify the physical definitions for the library, do that by clicking on the navigate button on the right of the LEF Files entry which should pop-up the LEF Files window. Navigate to the lib directory (that you just linked into your tutorial directory, in my case at ../lib) then click on osu025_stdcells.lef, and finally on Add, then on Close

Then we need to specify the timing definitions for the library, do that by clicking on the navigate button on the right of the Common Timing Libraries entry which should pop-up the Timing Files window (note that more advanced libraries will have Max Timing and Min Timing Libraries in order to be able to do “corner analysis”, not just nominal analysis). Navigate to the lib directory (that you just linked into your tutorial directory, in my case at ../lib) then click on osu018_stdcells.tlf, and finally on Add, then on Close

Normally, if this was a full chip design, we would also have to specify the I/O pad information now by the IO Assignment File, but for now we will not use I/O pads. Your Design Import pop-up window should look like this now

Now click on the Advanced tab at the top followed by Power on the left. Fill in vdd for Power Nets and gnd for Ground Nets (out of curiosity you can check that indeed these are the names of the power and gnd nets in your Verilog netlist by opening the file in a text editor).

Now click on the IPO/CTS and fill buf for Buffer Name/Footprint and inv for Inverter Name/Footprint (out of curiosity you can check that indeed these are the footprint names by examining the .tlf file in the lib directory). Also click on Generate Footprint Based on Functional Equivalence.

Finally click on OK in your Design Import pop-up window. Get familiar with some of the widgets, for example the Design Browser widget (the 7th from the right, top row) lets you see the design hierarchy, etc.

Now we need to specify floorplaning information. Since our design is simple and flat there is not much that needs to be done, but in general now is the time to decide how the big blocks that make up the design should be placed with respect to each other. Click on Floorplan -> Specify Floorplan and change Core to Left, Core to Right, Core to Top and Core to Bottom to 100.00 (default is 0.00). Also, change Ratio (H/W) to 1.

Click on Apply and the floorplan should change to reflect the 100 micron periphery around the core.

Now you can also play with the aspect ratio on the Specify floorplan window, change that to 0.5, click Apply, then to 2, click Apply again, finally back to 1 and click Apply. Note how the number of rows in your floorplan changes from 5 (for 1) to 7 (for 2) to 3 (for 0.5). It is a good idea to save your design from time to time by Design -> Save Design As -> SoCE…

The next step is to create the power and ground connections, but first you have to specify the nets. Click on Floorplan -> Connect Global Nets… and then fill the pop-up window connecting pin vdd to global net vdd, and pin gnd to global net gnd, making sure the button Apply All is checked (need to do this one at a time by adding to list). Click Apply, then Check (make sure there are no warnings here), then Cancel to close the pop-up.

Now we can finally create the power distribution for our design. Click Power -> Power Planning -> Add Rings…. Choose metal 4 and metal 5 with the width and spacing of 8 and 1 and with offset of 1, then click Apply, followed by Cancel.

Click Power -> Power Planning -> Add Stripes…. Choose metal 5 with the width and spacing of 8 and 1 and with Y from bottom of 30, then click Apply, followed by OK.

Then, in order to route the rest of the power distribution click Route -> Special Route…, deselect Pad pins, then click Apply, followed by OK.

Now your floorplan should look like this.

It is time to place our cells, go to Place -> Standard Cells and Blocks… then click Apply, followed by OK.

In order to avoid DRC errors later, it is usually a good idea to place fill cells to fill in the gaps between your placed standard cells. To do this, go to Place -> Filler -> Add Filler… and in the window that comes up, press the top Select button next to the Cell Name(s) form. A window will pop up and in the right column you should see a line that says FILL. Select FILL from the right side, click Add followed by OK. In the Add Filler window you should now see FILL in the top form. Click Apply followed by OK.

Now, if you click on the Physical View widget (on the right of the second row of the widget menu, right to the left of All Colors, it looks like a transistor layout) you will see your placed design.

Finally we can also route our design, go to Route -> NanoRoute -> Route… and click Apply followed by OK.


And now your design should be also routed:

Since we don’t have pads in our design the tools route the primary inputs and outputs to the periphery of the floorplan such that they can in principle be connected in a hierarchical fashion to other blocks.

Now that you have completed the physical design of your circuit it is a good idea to verify it by running a DRC check. To do this in SoC Encounter, select Verify -> Verify Geometry… and then click OK. Make sure there are no violations listed in the terminal window.

Congratulations, this is the end of the SoC Encounter tutorial.



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