Lib4U

‎"Behind every stack of books there is a flood of knowledge."

Kees Goossens’s Publications Page

kees_goossens

Here is a list of my publications, in reverse chronological order. Note that the copyright on some of the files below may not be owned by me, please comply with the owner’s conditions. Files are provided to allow browsing of documents, much like in a paper library. Let me know if you have problems retrieving a file.

The CompSOC team, platform, and research are now on the web at this CompSOC site.


To get started

A good two-page/executive-level overview of the CompSOC platform and accompanying SDF3 design flow is given here.
A good eight-page overview of the CompSOC platform concepts and design flow is given here.

The CompSOC team, platform, and research are now on the web at this CompSOC site.

Two essential components of our CompSOC platform are described in the following two books:

  • “On-Chip Interconnect with aelite: Composable and Predictable Systems” by Andreas Hansson and Kees Goossens
    contains the concepts, architectures, and tools of the Aelite and Aethereal networks on chip.
  • “Memory Controllers for Real-Time Embedded Systems” by Benny Akesson and Kees Goossens
    contains the concepts, architecture, and tools of the Predator real-time memory controller.

They are published by Springer in their Embedded Systems Series. For more information click on the images of the books.
 

The best overview or introductory articles of our research approach to predictable and composable systems can be found in the following papers.

The CompSOC platform is a research platform developed by the Eindhoven University of Technology and the Delft University of Technology, both in the Netherlands.

Aim

CompSOC aims to reduce system complexity through two techniques

  • composability: each application can be developed, verified, and executed in isolation.
    The complete absence of any interference (timing, energy/power, value domains) between applications allows different applications to be designed and verified independently.  Integration of multiple applications on the same platform, and switching them on and off at run time is guaranteed to not impact other applications in any way.  To implement composability we offer avirtual execution platform to each application, in which it can perform its own task scheduling and power management.  Different applications can use different models of computation (dataflow, Kahn process networks, and so on), since they are isolated in their own virtual platforms
  • predictability: real-time applications can be implemented in CompSOC since each virtual platform has well-defined timing properties.  In fact, if cyclo-static dataflow (CSDF) is used, the SDF3 tools provide automated mapping to the CompSOC platform, which includes: binding tasks to processors, local state to local memories, communication channels to network-on-chip (NOC) connections and local and remote memories, computing scheduling settings for RTOS, NOC, memory controllers, etc.

Platform

The CompSOC platform consists of

  • the Aethereal / aelite / daelite network on chip
  • multiple microBlaze tiles with local memories and DMAs
  • the microBlazes optionally run the CompOSe real-time operating system (RTOS)
  • the Predator real-time DRAM memory scheduler and controller

CompSOC platforms are prototyped on Xilinx FPGA boards, and (partially) in SystemC.

An advanced tool chain provides automated generation of

  • application-specific networks on chip (RTL VHDL, SystemC, C drivers)
  • application-specific arbitration for shared memories (SystemC, C drivers)
  • CompSOC hardware instances (multiple microBlaze tiles, NOC, multiple shared memories)
  • automated mapping of cyclo-static dataflow applications (CSDF) on the CompSOC platform.
    The open-source SDF3 tools are used for this.
  • automated DRAM power estimation (open-source DRAMPower)

A brief (two-page) introduction can be found here, and a longer (eight-page) version is here.

Research

System-on-Chip (SoC) design becomes increasingly complex, as a growing number of applications are integrated in such systems. These applications have mixed time-criticality, i.e., some have firm-, some soft-, and some non-real-time requirements. Executing mixed time-criticality applications on a complex SoC in an energy-efficient manner leads to the following problems. First, to reduce cost, platform resources, e.g., processors, interconnect, memories, are shared between applications. However, sharing causes interference between applications, making their behaviors interdependent.This results in two problems for SoC design and verification: 1) accurate system-level simulation and several approaches to formal verificationare infeasible, because of the explosion in the number of possible combinations of applications, inputs, and resource states and 2) verification becomes a circular process that must be repeated if an application is added, removed, or modified, making integration and verification dominant parts of SoC development, in terms of time and money. Second, energy management is traditionally regarded as a system-level issue. Management policies are hence generally developed for entire SoCs. Applications with different time-criticality inherently have different requirements, hence utilizing a single policy for an entire SoC leads to energy-inefficient execution, or even violation of real-time constraints.

The CompSOC platform addresses these problems by executing each application in an independent virtual platform. The virtual platforms are composable, i.e., cannot affect each other’s behaviors. In the temporal domain an application’s actual execution never varies by even a single clock cycle. Similarly, the energy and power behaviors of applications are composable. As a result, applications can be designed, developed, verified, and executed in isolation. Composable virtualization alleviates the verification problem in the mixed-time criticality domain in two ways: 1) verification becomes a non-circular process, and 2) the time required by simulation based verification is reduced, since only a single application in its virtual platform has to be simulated. Furthermore, energy usage can be managed per-application. Each application receives an independent energy and/or power budget, which it can manage with its own application-specific policy. Designers can optimize their application’s energy consumption using their virtual platform’s specification, independently of the development of other applications for the same platform.

The virtual platforms are also predictable, meaning that all interference is bounded. This makes them virtualized also in terms of performance bounds, which enables firm real-time applications to be verified using formal performance analysis frameworks. Currently, we are utilizing the SDF3 design-flow to automatically analyze firm real-time applications, and map them on a virtual platform. Furthermore, CompSOC provides a uniform execution model for several computation models, namely, dataflow, Kahn Process Networks, and simple threads, to suit each of the firm-, soft-, and no real-time domains.

The CompSOC Team

The CoMPSoC platform would not have been possible without the contributions of many people. Below is a list of the currently active project members at Eindhoven University of Technology and Delft University of Technology, respectively.

a photo, duh

A team meeting in January 2013.

Eindhoven University of TechnologyElectronic Systems group

  • Prof. Kees Goossens (team leader)
  • Benny Akesson (post doc.)
  • Sander Stuijk (assistant Prof.)
  • Sven Goossens (PhD)
  • Manil Dev Gomony (PhD)
  • Radu Stefan (post-doc)
  • Martijn Koedam (PhD)
  • Shubhendu Sinha (PhD)
  • Jun Zhu (post doc.)

Delft University of TechnologyComputer Engineering group

  • Andrew Nelson (PhD)
  • Ashkan Beyranvand Nejad (PhD)
  • Karthik Chandrasekar (PhD)
  • Davit Mirzoyan (PhD)

We are always looking for good new team members (PhD candidates, MSc thesis projects, etc.).
Fill out this registration form and contact Kees Goossens (TU Eindhoven) for more information.

 

the team

A team meeting in May 2012.


All my publications, in reverse chronological order

To be precise, theses, books, book chapters, journal articles, and peer-reviewed and invited conference papers. Not included are patent (applications), local conferences, conferences without proceedings, and posters.


2013


  • “Process-Variation Aware Mapping of Best-Effort and Real-Time Streaming Applications to MPSoCs”
    Davit Mirzoyan, Benny Akesson, Kees Goossens
    To appear in ACM Transactions on Embedded Computing Systems (TECS), 2013.
  1.  “Hardware/Software platform for QoS Bridging over Multi-Chip NoC-Based Systems”
    Ashkan Beyranvand Nejad, Anca Molnos, Matias Escudero Martinez, and Kees Goossens.
    Elsevier J. on Parallel Compututing, 2013.
  2. “Virtual Execution Platforms for Mixed-Time-Criticality Systems: The CompSOC Architecture and Design Flow”
    Kees Goossens, Arnaldo Azevedo, Karthik Chandrasekar, Manil Dev Gomony, Sven Goossens, Martijn Koedam, Yonghui Li, Davit Mirzoyan, Anca Molnos, Ashkan Beyranvand Nejad, Andrew Nelson, and Shubhendu Sinha.
    To appear in ACM SIGBED, 2013.
  3. “Towards Variation-Aware System-Level Power Estimation of DRAMs: An Empirical Approach”
    Karthik Chandrasekar, Christian Weis, Benny Akesson, Norbert Wehn, Kees Goossens
    In Proc. Design Automation Conference (DAC), June 2013.
  4. “TeMNOT: A Test Methodology for the Non-Intrusive Online Testing of FPGA with Hardwired Network on Chip”
    Aqeel Wahlah and Kees Goossens.
    In Microprocessors and Microsystems (MICPRO), Elsevier, May, 2013.
  5. “System and Circuit Level Power Modeling of Energy-Efficient 3D-Stacked Wide I/O DRAMs”
    Karthik Chandrasekar, Christian Weis, Benny Akesson, Norbert Wehn, and Kees Goossens.
    In Proc. Design, Automation and Test in Europe Conference and Exhibition (DATE), March 2013.
  6. “Architecture and optimal configuration of a real-time multi-channel memory controller”
    Manil Dev Gomony, Benny Akesson, and Kees Goossens.
    In Proc. Design, Automation and Test in Europe Conference and Exhibition (DATE), March 2013.
  7. “Conservative open-page policy for mixed time-criticality memory controllers”
    Sven Goossens, Benny Akesson, and Kees Goossens.
    In Proc. Design, Automation and Test in Europe Conference and Exhibition (DATE), March 2013.
  8. “Throughput-constrained voltage and frequency scaling for real-time heterogeneous multiprocessors.”
    Pengcheng Huang, Orlando Moreira, Kees Goossens, and Anca Molnos.
    In Proc. Symposium On Applied Computing (SAC), March 2013.


    2012


  9. “Comparative analysis of soft and hard on-chip interconnects for FPGAs”
    Jae Young Hur, Kees Goossens, Lotfi Mhamdi, and Muhammad Wahlah.
    In IET Computers & Digital Techniques, vol 6(1), December 2012.
  10. “Virtual execution platforms for mixed-time-criticality applications: The CompSOC architecture and design flow” [no proceedings, journal version upcoming]
    Kees Goossens, Arnaldo Azevedo, Karthik Chandrasekar, Manil Dev Gomony, Sven Goossens, Martijn Koedam, Yonghui Li, Davit Mirzoyan, Anca Molnos, Ashkan Beyranvand Nejad, Andrew Nelson, and Shubhendu Sinha.
    In Proc. Workshop on Compositional Theory and Technology for Real-Time Embedded Systems (CRTS), December 2012.
  11. “Hardware / Software Virtualization for the Reconfigurable Multicore Platform”
    M. Ferger, M. Al Kadi, M. Hubner, M. Koedam, S. Sinha, K. Goossens, G. Marchesan Almeida, J. Rodrigo Azambuja, J. Becker.
    In Proc. Int’l Conference on Embedded and Ubiquitous Computing, December 2012.
  12. “Hardware design and implementation of a network-on-chip based load balancing switch fabric”
    Turhan Karadeniz, Lotfi Mhamdi, Kees Goossens, and J.J. Garcia-Luna-Aceves.
    In Proc. Int’l Conference on Reconfigurable Computing and FPGAs (ReConFig), December 2012.
  13. “Power versus quality trade-offs for adaptive real-time applications”
    Andrew Nelson, Anca Molnos, and Kees Goossens.
    In Proc. Embedded Systems for Real-Time Multimedia (ESTIMedia), October 2012 .
  14. “Embedded computer architecture laboratory: A hands-on experience programming embedded systems with resource and energy constraints”
    Andrew Nelson, Anca Molnos, Ashkan Beyranvand Nejad, Davit Mirzoyan, Sorin Cotofana, and Kees Goossens.
    In Proc. Workshop on Embedded Systems Education (WESE), October 2012 .
  15. “Architecture and Design Flow for a Debug Event Distribution Interconnect”
    Arnaldo Azevedo, Bart Vermeulen and Kees Goossens.
    In Proc. Int’l Conference on Computer Design (ICCD), September 2012 .
  16. “Composable virtual memory for an embedded SoC”
    Cor Meenderinck, Anca Molnos, and Kees Goossens.
    In Proc. Euromicro Symposium on Digital System Design (DSD), September 2012 .
  17. “A predictor-based power-saving policy for DRAM memories”
    Gervin Thomas, Karthik Chandrasekar, Benny Akesson, Ben Juurlink, and Kees Goossens.
    In Proc. Euromicro Symposium on Digital System Design (DSD), September 2012 .
  18. “dAElite: A TDM NoC supporting QoS, multicast, and fast connection set-up”
    Radu Stefan, Anca Molnos, and Kees Goossens.
    In IEEE Transactions on Computers, 2012.
  19. “Towards future adaptive multiprocessor systems-on-chip: an innovative approach for flexible architectures”
    Fabrice Lemonnier, Philippe Millet, Gabriel Marchesan Almeida, Michael Hubner, Jurgen Becker, Sebastien Pillement, Olivier Sentieys, Martijn Koedam, Shubhendu Sinha, Kees Goossens, Christian Piguet, Marc-Nicolas Morgan, and Romain Lemaire.
    In Proc. Int’l Conference on Embedded Computer Systems: Architectures, MOdeling and Simulation (SAMOS), July 2012.
  20. “Run-time power-down strategies for real-time SDRAM memory controllers”
    Karthik Chandrasekar, Benny Akesson, and Kees Goossens.
    In Proc. Design Automation Conference (DAC), June 2012.
  21. “Decoupled inter- and intra-application scheduling for composable and robust embedded MPSoC platforms”
    Anca Molnos, Ashkan Beyranvand Nejad, Ba Thang Nguyen, Sorin Cotofana, and Kees Goossens.
    In Proc. Workshop on Mapping of Applications to MPSoCs (MAP2MPSOC), May 2012.
  22. “Process-variation aware mapping of real-time streaming applications to MPSoCs for improved yield”
    Davit Mirzoyan, Benny Akesson, and Kees Goossens.
    In Proc. Int’l Symposium on Quality Electronic Design (ISQED), March 2012.
  23. “Memory-map selection for firm real-time memory controllers” (poster)
    Sven Goossens, Tim Kouters, Benny Akesson, and Kees Goossens.
    In Proc. Design, Automation and Test in Europe Conference and Exhibition (DATE), March 2012.
  24. “DRAM selection and configuration for real-time mobile systems”
    Manil Dev Gomony, Christian Weis, Benny Akesson, Norbert Wehn, and Kees Goossens.
    In Proc. Design, Automation and Test in Europe Conference and Exhibition (DATE), March 2012.
  25. “A TDM NoC supporting QoS, multicast, and fast connection set-up”
    Radu Stefan, Anca Molnos, Angelo Ambrose, and Kees Goossens.
    In Proc. Design, Automation and Test in Europe Conference and Exhibition (DATE), March 2012.
  26. “Customization of on-chip network interconnects and experiments in FPGAs”
    Jae Young Hur, Todor Stefanov, Stephan Wong, and Kees Goossens.
    In IET Computers & Digital Techniques, vol 6(1), Jan 2012.
  27. “Online allocation for contention-free-routing NoCs”
    Radu Stefan and Ashkan Beyranvand Nejad and Kees Goossens.
    In Proc. Interconnection Network Architecture: On-Chip, Multi-Chip (INA-OCMC), Jan 2012.


    2011


  28. “Enhancing the security of time-division-multiplexing networks-on-chip through the use of multipath routing”
    Radu Stefan and Kees Goossens.
    In Proc. Int’l Workshop on Network on Chip Architectures (NOCARC), December 2011.
  29. “Memory controllers for high-performance and real-time MPSoCs — Requirements, architectures, and future trends”
    Benny Akesson, Po-Chun Huang, Fabien Clermidy, Denis Dutoit, Kees Goossens, Yuan-Hao Chang, Tei-Wei Kuo, Pascal Vivet, and Drew Wingard.
    In Int’l Conf. on Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2011.
  30. “Time-predictable and composable architectures for dependable embedded systems”
    Saddek Bensalem, Kees Goossens, Christoph M. Kirsch, Roman Obermaisser, Edward A. Lee, and Joseph Sifakis.
    In Proc. Int’l Conference on Embedded software (EMSOFT), October 2011.
  31. “Memory Controllers for Real-Time Embedded Systems” [springerlink]
    Benny Akesson and Kees Goossens.
    Embedded Systems Series. Springer, September 2011.
    For more information see here.
  32. “Automatic generation of efficient predictable memory patterns”
    Benny Akesson, Williston Hayes Jr., and Kees Goossens.
    In Proc. Int’l Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), August 2011.
  33. “Resource-efficient real-time scheduling using credit-controlled static-priority arbitration”
    Firew Siyoum, Benny Akesson, Sander Stuijk, Kees Goossens, and Henk Corporaal.
    In Proc. Int’l Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), August 2011.
  34. “Improved power modeling of DDR SDRAMs”
    Karthik Chandrasekar, Benny Akesson, and Kees Goossens.
    In Proc. Euromicro Symposium on Digital System Design (DSD), August 2011.
  35. “Power minimisation for real-time dataflow applications”
    Andrew Nelson, Orlando Moreira, Anca Molnos, Sander Stuijk, Ba Thang Nguyen, and Kees Goossens.
    In Proc. Euromicro Symposium on Digital System Design (DSD), August 2011.
  36. “PUMA: Placement unification with mapping and guaranteed throughput allocation on an FPGA using a hardwired NoC”
    Muhammad Aqeel Wahlah and Kees Goossens.
    In Proc. Euromicro Symposium on Digital System Design (DSD), August 2011.
  37. “A non-intrusive online FPGA test scheme using a hardwired network on chip”
    Muhammad Aqeel Wahlah and Kees Goossens.
    In Proc. Euromicro Symposium on Digital System Design (DSD), August 2011.
  38. “Composable Power Management with Energy and Power Budgets per Application”
    Andrew Nelson, Anca Molnos, and Kees Goossens.
    In Proc. Int’l Conference on Embedded Computer Systems: Architectures, MOdeling and Simulation (SAMOS), July 2011.
  39. “Editorial: Special Issue on Networks-on-Chip: Design Flows and Case Studies”
    Kees Goossens and Radu Marculescu.
    In Springer Journal of Design Automation for Embedded Systems (DAEM), 2011.
  40. “A quantitative evaluation of a network-based interconnect for multi-core consumer multimedia applications”
    Andreas Hansson and Kees Goossens.
    In Springer Journal of Design Automation for Embedded Systems (DAEM), 2011.
  41. “A TDM slot allocation flow based on multipath routing in NoCs”
    Radu Stefan and Kees Goossens.
    In Microprocessors and Microsystems (MICPRO), Elsevier, 2011.
  42. “Design and Implementation of an Operating System for Composable Processor Sharing”
    Andreas Hansson, Marcus Ekerhult, Anca Molnos, Aleksandar Milutinovic, Andrew Nelson, Jude Ambrose, and Kees Goossens.
    In Microprocessors and Microsystems (MICPRO), Elsevier, 2011.
  43. “Interactive debugging of systems on chip with multiple clocks”
    Bart Vermeulen and Kees Goossens.
    In Design and Test of Computers, Special issue on Transaction-Level Validation of Multicore Architectures, May/June 2011.
    Version with colour graphs.
  44. “Architectures and Modeling of Predictable Memory Controllers for Improved System Integration”
    Benny Akesson and Kees Goossens.
    In Proc. Design, Automation and Test in Europe Conference and Exhibition (DATE), 2011.
  45. “An FPGA Bridge Preserving Traffic Quality of Service for On-Chip Network-Based Systems”
    Ashkan Beyranvand Nejad, Matias Escudero Martinez and Kees Goossens.
    In Proc. Design, Automation and Test in Europe Conference and Exhibition (DATE), 2011.
  46. “Optimal scheduling of switched FlexRay networks”
    Thijs Schenkelaars, Bart Vermeulen, Kees Goossens.
    In Proc. Design, Automation and Test in Europe Conference and Exhibition (DATE), 2011.
  47. “An improved algorithm for slot selection in the Aethereal network-on-chip”
    Radu Stefan and Kees Goossens.
    In Proc. Interconnection Network Architecture: On-Chip, Multi-Chip (INA-OCMC), 2011.


    2010


  48. “Checking pipelined distributed global properties for post silicon debug”
    Erik Larsson, Bart Vermeulen, and Kees Goossens.
    In Proc. Workshop on RTL and high level testing (WRTLT), December 2010.
  49. “Composability and predictability for independent application development, verification, and execution”
    Benny Akesson, Anca Molnos, Andreas Hansson, Jude Ambrose Angelo, and Kees Goossens.
    In Michael Huebner and Juergen Becker, editors, Multiprocessor System-on-Chip — Hardware Design and Tool Integration, Circuits and Systems, chapter 2. Springer, November 2010.
    [springerlink]
  50. “On-Chip Interconnect with aelite: Composable and Predictable Systems” [springerlink]
    Andreas Hansson and Kees Goossens.
    Embedded Systems Series. Springer, November 2010.
    For more information see here.
  51. “Conservative application-level performance analysis through simulation of MPSoCs”
    Andrew Nelson, Andreas Hansson, Henk Corporaal, Kees Goossens.
    In Proc. Embedded Systems for Real-Time Multimedia (ESTIMedia), October 2010.
  52. “Composable Dynamic Voltage and Frequency Scaling and Power Management for Dataflow Applications”
    Kees Goossens, Dongrui She, Aleksandar Milutinovic, Anca Molnos.
    In Proc. Euromicro Symposium on Digital System Design (DSD), September 2010.
  53. “Classification and Analysis of Predictable Memory Patterns”
    Benny Akesson, Williston Hayes Jr., and Kees Goossens.
    In Proc. Embedded and Real-Time Computing Systems and Applications (RTCSA), August 2010.
  54. “On-chip Network Interfaces supporting automatic burst write creation, posted writes and read prefetch”
    Radu Stefan, Jason de Windt, Kees Goossens.
    In Proc. Int’l Conference on Embedded Computer Systems: Architectures, MOdeling and Simulation (SAMOS), July 2010.
  55. “Bandwidth Analysis for Reusing Functional Interconnect as Test Access Mechanism”
    Ardy van den Berg, Pengwei Ren, Erik Jan Marinissen, Georgi Gaydadjiev, and Kees Goossens.
    In Springer Journal of Electronic Testing, July 2010.
  56. “Obtaining consistent global state dumps to interactively debug systems on chip with multiple clocks”
    Bart Vermeulen and Kees Goossens.
    In Proc. International High Level Design Validation and Test Workshop (HLDVT), June 2010.
  57. “Debugging Multi-Core Systems on Chip”
    Bart Vermeulen, and Kees Goossens.
    In George Kornaros, editor, Multi-Core Embedded Systems, chapter 5, pages 153–198. CRC Press/Taylor & Francis Group, 2010.
    The chapter can be found here. The book can be found here
  58. “The Aethereal Network on Chip after Ten Years: Goals, Evolution, Lessons, and Future”
    Kees Goossens and Andreas Hansson.
    In Proc. Design Automation Conference (DAC), June 2010.
    HiPEAC paper award
  59. “A Composable, Energy-Managed, Real-Time MPSOC Platform”
    Anca Molnos, Jude Angelo Ambrose, Andrew Nelson, Radu Stefan, Sorin Cotofana, Kees Goossens.
    In Proc. Int’l Conference on Optimization of Electrical and Electronic Equipment (OPTIM).
  60. “Distributed architecture for checking global properties during post silicon debug”
    Erik Larsson, Bart Vermeulen, and Kees Goossens.
    In Proc. European Test Symposium (ETS), May 2010.
  61. “Buffered Crossbar Fabrics based on Networks on Chip”
    Lotfi Mhamdi, Iria Varela Senin, and Kees Goossens.
    In Proc. Annual Conference on Communication Networks and Services Research (CNSR), May 2010.
  62. “Composable processor virtualization for embedded systems”
    Anca Molnos, Aleksandar Milutinovic, Dongrui She, and Kees Goossens.
    In Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS), Lecture Notes in Computer Science (LNCS). Springer, January 2010.


    2009


  63. “Composable and persistent-state application swapping on FPGAs using hardwired network on chip”
    Muhammad Aqeel Wahlah, and Kees Goossens.
    In Proc. Int’l Conference on Reconfigurable Computing and FPGAs (ReConFig), December 2009.
  64. “Efficient multicast support in buffered crossbars using networks on chip”
    Iria Varela Senin, Lotfi Mhamdi, and Kees Goossens.
    In Proc. Global Telecommunications Conference, December 2009.
  65. “An on-chip interconnect and protocol stack for multiple communication paradigms and programming models”
    Andreas Hansson and Kees Goossens.
    In Int’l Conf. on Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2009.
  66. “Dynamic Workload Peak Detection For Slack Management”
    Aleksandar Milutinovic, Kees Goossens, and Gerard Smit.
    In Proc. Int’l Symposium on Systems on Chip (SoC), October 2009.
  67. “Multi-Path Routing in Time-Division-Multiplexed Networks on Chip”
    Radu Stefan and Kees Goossens.
    In Proc. IFIP Int’l Conference on Very Large Scale Integration (VLSI-SoC), October 2009.
  68. “Efficient Service Allocation in Hardware Using Credit-Controlled Static-Priority Arbitration”
    Benny Akesson, Liesbeth Steffens, and Kees Goossens.
    In Proc. Embedded and Real-Time Computing Systems and Applications (RTCSA), August 2009.
  69. “Conservative dynamic energy management for real-time dataflow applications mapped on multiple processors”
    Anca Molnos and Kees Goossens.
    In Proc. Euromicro Symposium on Digital System Design (DSD), August 2009.
  70. “Composable resource sharing based on latency-rate servers”
    Benny Akesson, Andreas Hansson, and Kees Goossens.
    In Proc. Euromicro Symposium on Digital System Design (DSD), August 2009.
  71. “Internet-router buffered crossbars based on networks on chip”
    Kees Goossens, Lotfi Mhamdi, and Iria Varela Senin.
    In Proc. Euromicro Symposium on Digital System Design (DSD), August 2009.
  72. “A network-on-chip monitoring infrastructure for communication-centric debug of embedded multi-processor SoCs”
    Bart Vermeulen and Kees Goossens.
    In Proc. Int’l Symposium on VLSI Design, Automation and Test (VLSI-DAT), 2009.
  73. “Modeling reconfiguration in a FPGA with a hardwired network on chip”
    Muhammad Aqeel Wahlah and Kees Goossens.
    In Proc. Reconfigurable Architecture Workshop (RAW), 2009.
  74. “aelite: A Flit-Synchronous Network on Chip with Composable and Predictable Services”
    Andreas Hansson, Mahesh Subbaraman, and Kees Goossens.
    In Proc. Design, Automation and Test in Europe Conference and Exhibition (DATE), April 2009.
  75. “A High-Level Debug Environment for Communication-Centric Debug”
    Kees Goossens, Bart Vermeulen, Ashkan Beyranvand Nejad.
    In Proc. Design, Automation and Test in Europe Conference and Exhibition (DATE), April 2009.
  76. “Editorial: Networks on Chips”
    Davide Bertozzi and Kees Goossens.
    In IET Computers & Digital Techniques, 2009.
  77. “Enabling Application-Level Performance Guarantees in Network-Based Systems on Chip by Applying Dataflow Analysis”
    Andreas Hansson, Maarten Wiggers, Arno Moonen, Kees Goossens, Marco Bekooij.
    In IET Computers & Digital Techniques, 2009.
  78. “CoMPSoC: A template for composable and predictable multi-processor system on chips”
    Andreas Hansson, Kees Goossens, Marco Bekooij, and Jos Huisken.
    ACM Transactions on Design Automation of Electronic Systems, 2009.


    2008


  79. “You can catch more bugs with transaction level honey”
    Miron Abramovici, Neal Stollon, Kees Goossens, Bart Vermeulen, Jack Greenbaum, and Adam Donlin.
    In Int’l Conf. on Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2008.
  80. “Performance analysis of soft and hard single-hop and multi-hop circuit-switched interconnects for FPGAs”
    Jae Young Hur, Kees Goossens, and Lotfi Mhamdi.
    In Proc. IFIP Int’l Conference on Very Large Scale Integration (VLSI-SoC), October 2008.
  81. “Impact of power-management granularity on the energy-quality trade-off for soft and hard real-time applications”
    Aleksandar Milutinovic, Kees Goossens, and Gerard Smit.
    In Proc. Int’l Symposium on Systems on Chip (SoC), October 2008.
  82. “Real-time scheduling using credit-controlled static-priority arbitration”
    Benny Akesson, Liesbeth Steffens, Eelke Strooisma, and Kees Goossens.
    In Proc. Embedded and Real-Time Computing Systems and Applications (RTCSA), August 2008.
  83. “Bandwidth Analysis for Reusing Functional Interconnect as Test Access Mechanism”
    Ardy van den Berg, Pengwei Ren, Erik Jan Marinissen, Georgi Gaydadjiev, and Kees Goossens.
    In Proc. European Test Symposium (ETS), May 2008.
  84. “Hardwired Networks on Chip in FPGAs to unify Data and Configuration Interconnects”
    Kees Goossens, Martijn Bennebroek, Jae Young Hur, and Muhammad Aqeel Wahlah.
    In Proc. Int’l Symposium on Networks on Chip (NOCS), April 2008.
  85. “Debugging Distributed-Shared-Memory Communication at Multiple Granularities in Networks on Chip”
    Bart Vermeulen, Kees Goossens, and Siddharth Umrani.
    In Proc. Int’l Symposium on Networks on Chip (NOCS), April 2008.
  86. “A monitoring-aware network-on-chip design flow”
    Calin Ciordas, Andreas Hansson, Kees Goossens, and Twan Basten.
    In Journal of Systems Architecture, March-April 2008.
  87. “Trade offs in the design of a router with both guaranteed and best-effort services for networks on chip”
    E. Rijpkema, K. G. W. Goossens, A. Radulescu, J. Dielissen, J. van Meerbergen, P. Wielage, and E. Waterlander.
    In Rudy Lauwerijns and Jan Madsen, editors, Design Automation, and Test in Europe. The Most Influential Papers of 10 Years DATE, Circuits and Systems, Chapter 2 (Networks on Chip). Springer, January 2008.
    DATE versionextended CDT journal version;


    2007


  88. “Comparison of an Aethereal network on chip and traditional interconnects – two case studies”
    Arno Moonen, Chris Bartels, Marco Bekooij, Rene van den Berg, Harpreet Bhullar, Kees Goossens, Patrick Groeneveld, Jos Huiskens, and Jef van Meerbergen.
    In Giovanni De Micheli, Salvador Mir, and Ricardo Reis, editors, VLSI-SoC: Research Trends in VLSI and Systems on Chip, number 249 in IFIP International Federation for Information Processing. Springer, 2007.
  89. “Predator: A predictable SDRAM memory controller”
    Benny Akesson, Kees Goossens, and Markus Ringhofer.
    In Int’l Conf. on Hardware/Software Codesign and System Synthesis (CODES+ISSS), October 2007.
  90. “Channel trees: Reducing latency by sharing time slots in time-multiplexed networks on chip”
    Andreas Hansson, Martijn Coenen, and Kees Goossens.
    In Int’l Conf. on Hardware/Software Codesign and System Synthesis (CODES+ISSS), October 2007.
  91. “The Future of Computing – Essays in Memory of Stamatis Vassiliadis”
    Koen Bertels, Sorin Cotofana, Georgi N. Gaydadjiev, Kees Goossens, Said Hamdioui, Arjan van Genderen, and Stephan Wong, editors.
    September 2007.
  92. “Wrapper design for the reuse of a bus, network-on-chip, or other functional interconnect as test access mechanism”
    Alexandre M. Amory, Kees Goossens, Erik Jan Marinissen, Marcelo Lubaszewski, and Fernando Moraes.
    In IET Computers & Digital Techniques, 2007.
  93. “A unified approach to mapping and routing on a network on chip for both best-effort and guaranteed service traffic”
    Andreas Hansson, Kees Goossens, and Andrei Radulescu.
    In VLSI Design – Special issue on Networks-on-Chip, Hindawi Publishing Corporation, 2007.
  94. “Avoiding message-dependent deadlock in network-based systems on chip”
    Andreas Hansson, Kees Goossens, and Andrei Radulescu.
    In VLSI Design – Special issue on Networks-on-Chip, Hindawi Publishing Corporation, 2007.
  95. “Trade-offs in the configuration of a network on chip for multiple use-cases”
    Andreas Hansson and Kees Goossens.
    In Proc. Int’l Symposium on Networks on Chip (NOCS), May 2007.
  96. “Transaction-based communication-centric debug”
    Kees Goossens, Bart Vermeulen, Remco van Steeden, and Martijn Bennebroek.
    In Proc. Intl Symposium on Networks on Chip (NOCS), May 2007.
  97. “Communication-centric SOC debug using transactions”
    Bart Vermeulen, Kees Goossens, Remco van Steeden, and Martijn Bennebroek.
    In Proc. European Test Symposium (ETS), May 2007.
  98. “Undisrupted quality-of-service during reconfiguration of multiple applications in networks on chip”
    Andreas Hansson, Martijn Coenen, and Kees Goossens.
    In Proc. Design, Automation and Test in Europe Conference and Exhibition (DATE), April 2007.
  99. “Congestion-controlled best-effort communication for networks-on-chip”
    Jan Willem van den Brand, Calin Ciordas, Twan Basten, and Kees Goossens.
    In Proc. Design, Automation and Test in Europe Conference and Exhibition (DATE), April 2007.


    2006


  100. “A buffer-sizing Algorithm for Networks on Chip using TDMA and credit-based end-to-end Flow Control”
    Martijn Coenen, Srinivasan Murali, Andrei Radulescu, Kees Goossens, and Giovanni De Micheli.
    In Int’l Conf. on Hardware/Software Codesign and System Synthesis (CODES+ISSS), October 2006.
    Second most-cited CODES+ISSS 2006 article
  101. “Transaction Monitoring in Networks on Chip: The On-Chip Run-Time Perspective” Calin Ciordas, Kees Goossens, Twan Basten, Andrei Radulescu, Andre Boon.
    In Proc. Symposium on Industrial Embedded Systems (IES), October 2006.
    Best paper award
  102. “Comparison of An Aethereal Network on Chip and A Traditional Interconnect for A Multi-Processor DVB-T System on Chip”
    Chris Bartels, Jos Huisken, Kees Goossens, Patrick Groeneveld, and Jef van Meerbergen.
    In Proc. IFIP Int’l Conference on Very Large Scale Integration (VLSI-SoC), October 2006.
  103. “A monitoring-aware NoC design flow”
    Calin Ciordas, Andreas Hansson, Kees Goossens, and Twan Basten.
    In Proc. Euromicro Symposium on Digital System Design, August 2006.
  104. “Network and transport layers in networks on chip”
    Israel Cidon and Kees Goossens
    In Giovanni De Micheli and Luca Benini, editors, Networks on Chips: Technology and Tools, The Morgan Kaufmann Series in Systems on Silicon, chapter 5, pages 147–202. Morgan Kaufmann, July 2006.
  105. “Mixed adaptation and fixed-reservation QoS for improving Picture Quality and Resource Usage of Multimedia (NoC) Chips”
    Milan Pastrnak, Peter H.N. de With, Calin Ciordas, Jef van Meerbergen, Kees Goossens
    In Proc. Int’l Symposium on Consumer Electronics (ISCE), Jun 2006.
  106. “Sixth International Conference on Applications of Concurrency to System Design (ACSD)”
    Kees Goossens and Laure Petrucci, editors.
    Turku, Finland, June 2006.
  107. “Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism”
    Alexandre M. Amory, Kees Goossens, Erik Jan Marinissen, Marcelo Lubaszewski, Fernando Moraes
    In Proc. European Test Symposium (ETS), May 2006.
  108. “NoC monitoring: Impact on the design flow”
    Calin Ciordas, Kees Goossens, Andrei Radulescu, Twan Basten
    In Proc. Int’l Symposium on Circuits and Systems (ISCAS), May 2006.
  109. “Networks on Chips for High-End Consumer-Electronics TV System Architectures”
    Frits Steenhof and Harry Duque and Bjorn Nilsson and Kees Goossens and Rafael Peset Llopis
    In Proc. of Design, Automation and Test Conference in Europe, March 2006.
  110. “A Methodology for Mapping Multiple Use-Cases on to Networks on Chip”
    Srinivasan Murali, Martijn Coenen, Andrei Radulescu, Kees Goossens, and Giovanni De Micheli
    In Proc. of Design, Automation and Test Conference in Europe, March 2006.
  111. “Mapping and Configuration Methods for Multi-Use-Case Networks on Chips”
    Srinivasan Murali, Martijn Coenen, Andrei Radulescu, Kees Goossens, and Giovanni De Micheli
    in Proc. Design Automation Conference. Asia and South Pacific (ASP-DAC), January 2006.


    2005


  112. “An Event-based Monitoring Service for Networks on Chip”
    Calin Ciordas, Twan Basten, Andrei Radulescu, Kees Goossens, and Jef van Meerbergen.
    ACM Transactions on Design Automation of Electronic Systems, 10(4), Oct 2005.
  113. “The Aethereal network on chip: Concepts, architectures, and implementations”
    Kees Goossens, John Dielissen, and Andrei Radulescu.
    IEEE Design and Test of Computers, Vol 22(5):414–421, Sept-Oct 2005.
  114. “A Unified Approach to Constrained Mapping and Routing on Network-on-Chip Architectures”
    Andreas Hansson, Kees Goossens, and Andrei Radulescu.
    In Int’l Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Sep 2005.
    Best paper award, and most-cited CODES+ISSS 2005 article
  115. “Networks on Chip for Consumer Electronics”
    Kees Goossens.
    In Proc. Int’l Summer School on Advanced Computer Architecture and Compilation for Embedded Systems (ACACES), Jul 2005.
  116. “Formal Methods for Networks on Chip”
    Kees Goossens.
    In Proc. Int’l Conference on Application of Concurrency to System Design (ACSD), Jun 2005.
  117. “Deadlock Prevention in the AEthereal Protocol” (longer technical note)
    Biniam Gebremichael, Frits Vaandrager, Miaomiao Zhang, Kees Goossens, Edwin Rijpkema, and Andrei Radulescu.
    In Proc. Working Conference on Correct Hardware Design and Verification Methods (CHARME), Oct 2005.
  118. “Building Predictable Systems on Chip: An Analysis of Guaranteed Communication in the AEthereal Network on Chip”
    Om Prakash Gangwal, Andrei Radulescu, Kees Goossens and Santiago Gonzalez Pestana, and Edwin Rijpkema.
    In Peter van der Stok, editor, Dynamic and Robust Streaming In and Between Connected Consumer-Electronics Devices. Springer, 2005.
  119. “Service-Based Design of Systems on Chip and Networks on Chip”
    Kees Goossens, Santiago Gonzalez Pestana, John Dielissen, Om Prakash Gangwal, Jef van Meerbergen, Andrei Radulescu, Edwin Rijpkema, and Paul Wielage.
    In Peter van der Stok, editor, Dynamic and Robust Streaming In And Between Connected Consumer-Electronics Devices. Springer, 2005.
  120. “A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification”
    Kees Goossens, John Dielissen, Om Prakash Gangwal, Santiago Gonzalez Pestana, Andrei Radulescu, and Edwin Rijpkema.
    Proceedings of Design, Automation and Test Conference in Europe, March 2005.
  121.  “An Efficient On-Chip Network Interface Offering Guaranteed Services, Shared-Memory Abstraction, and Flexible Network Programming”
    Andrei Radulescu, John Dielissen, Santiago Gonzalez Pestana, Om Gangwal, Edwin Rijpkema, Paul Wielage, and Kees Goossens.
    IEEE Transactions on CAD of Integrated Circuits and Systems, 24(1), January 2005.


    2004


  122. “An Event-based Network-on-Chip Monitoring Service”
    Calin Ciordas, Twan Basten, Andrei Radulescu, Kees Goossens, and Jef van Meerbergen.
    International High Level Design Validation and Test Workshop (HLDVT), November 2004.
  123.  “An Efficient On-Chip Network Interface Offering Guaranteed Services, Shared-Memory Abstraction, and Flexible Network Programming”
    Andrei Radulescu, John Dielissen, Kees Goossens, Edwin Rijpkema, and Paul Wielage.
    Proceedings of Design, Automation and Test Conference in Europe, February 2004.
  124. “Cost-Performance Trade-offs in Networks on Chip: A Simulation-Based Approach”
    Santiago Gonzalez Pestana, Edwin Rijpkema, Andrei Radulescu, Kees Goossens, Om Prakash Gangwal.
    Proceedings of Design, Automation and Test Conference in Europe, February 2004.
  125. “Interconnect and Memory Organization in SOCs for advanced Set-Top Boxes and TV — Evolution, Analysis, and Trends”
    Kees Goossens, Om Prakash Gangwal, Jens Roever, A. P. Niranjan.
    In Interconnect-Centric Design for Advanced SoC and NoC, Jari Nurmi, Hannu Tenhunen, Jouni Isoaho, Axel Jantsch, editors. Kluwer, April, 2004.
  126. “Communication Services for Networks on Silicon”
    Andrei Radulescu and Kees Goossens.
    In Domain-Specific Processors: Systems, Architectures, Modeling, and Simulation, Shuvra Bhattacharyya and Ed Deprettere and Juergen Teich, editors. Marcel Dekker, 2004.


    2003


  127. “Concepts and Implementation of the Philips Network-on-Chip”
    John Dielissen, Andrei Radulescu, Kees Goossens, and Edwin Rijpkema.
    IP-Based SOC Design, November, 2003.
  128. “Bringing Communication Networks On Chip: Test and Verification Implications”
    Bart Vermeulen and John Dielissen and Kees Goossens and Calin Ciordas.
    IEEE Communications Magazine, September, 2003.
  129. “Trade-Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip”
    E. Rijpkema and K. Goossens and A. Radulescu, J. Dielissen and van Meerbergen, J. and P. Wielage and E. Waterlander.
    IEE Proceedings: Computers and Digital Techniques, September 2003.
  130. “Guaranteeing the quality of services in networks on chip”
    Kees Goossens, John Dielissen, Jef van Meerbergen, Peter Poplavko, Andrei Radulescu, Edwin Rijpkema, Erwin Waterlander, and Paul Wielage.
    In Networks on Chip, Axel Jantsch and Hannu Tenhunen, editors. Kluwer, March 2003.
  131. “Trade offs in the design of a router with both guaranteed and best-effort services for networks on chip”
    E. Rijpkema, K. G. W. Goossens, A. Radulescu, J. Dielissen, J. van Meerbergen, P. Wielage, and E. Waterlander.
    In Proceedings of Design, Automation and Test Conference in Europe (DATE), March 2003.
    Selected as one of the 30 most influential papers of 10 years of DATE


    2002


  132. “Networks on Silicon: Blessing or Nightmare?”
    Paul Wielage and Kees Goossens.
    In Euromicro Symposium On Digital System Design (DSD 2002), Dortmund, Germany, September 2002.
  133. “C-HEAP: A Heterogeneous Multi-processor Architecture Template and Scalable and Flexible Protocol for the Design of Embedded Signal Processing Systems”
    Andre Nieuwland, Jeffrey Kang, Om Prakash Gangwal, Ramanathan Sethuraman, Natalino Busa, Kees Goossens, Rafael Peset Llopis, and Paul Lippens.
    In Design automation for Embedded Systems, Vol 7(3): 229–266, 2002, Kluwer.
  134. “The Cost of Communication Protocols and Coordination Languages in Embedded Systems”
    K.G.W. Goossens and O.P. Gangwal.
    In Coordination’2002, April, 2002.
  135. “Networks on Silicon: Combining Best-Effort And Guaranteed Services”
    K. Goossens, J. van Meerbergen, A. Peeters, and P. Wielage.
    In Design automation and test conference (DATE), March, 2002.


    2001


  136. “A Router Architecture for Networks on Silicon”
    Edwin Rijpkema, Kees Goossens, and Paul Wielage.
    In Progress 2001, second workshop on embedded systems, November, 2001
  137. “Towards a model for making a trade-off between QoS and costs”
    Lodewijk T. Smit, Gerard J.M. Smit, Paul J.M. Havinga, Jos A. Huisken, Kees G.W. Goossens, and John T.M.H. Dielissen.
    In CTIT workshop, Mobile Communications: in perspective, February, 2001
  138. “A Protocol And Memory Manager For On-Chip Communication”
    K. G. W. Goossens.
    In International Symposium on Circuits and Systems, May 2001.


    1998


  139. “The Petrol Approach to High-Level Power Estimation”
    R. Peset Llopis and K. G. W. Goossens.
    In International Symposium on Low Power Electronics and Design (ISLPED), August 1998.


    1995


  140.  “Reasoning About VHDL Using Operational and Observational Semantics”
    K. G. W. Goossens.
    In Correct Hardware Design Methodologies (CHARME), March 1995.


  141. “The Formalisation of a Hardware Description Language in a Proof System: Motivation and Applications”
    K. G. W. Goossens.
    In Proceedings of the XIII Conference of the Brazilian Computer Society, September 1993.
  142. “Structure and Behaviour in Hardware Verification”
    K. G. W. Goossens.
    In Higher Order Logic Theorem Proving and Its Applications (HOL), August 1993.
  143. “Embedding Hardware Description Languages in Proof Systems”
    K. G. W. Goossens.
    PhD thesis, May 1993.
    pdf [original format] abstract DOI


    1992


  144. “Operational Semantics Based Formal Symbolic Simulation”
    K. G. W. Goossens.
    In Higher Order Logic Theorem Proving and Its Applications (HOL), September 1992.


    1991


  145. “Embedding a CHDDL in a Proof System”
    K. G. W. Goossens.
    In Advanced Research Workshop on Correct Hardware Design Methodologies (CHARME), June 1991.


Public Technical Notes

  • “Comparison of custom topology networks against rigid interconnects”
    Radu Stefan, Ioannis Sourdis, Georgi Gaydadjiev, and Kees Goossens.
    Technical Report CE-TR-2008-01, Computer Engineering, Delft University of Technology, February 2008.
  1.  “Reasoning About VHDL Using Operational and Observational Semantics”
    K. G. W. Goossens.
    DSI technical report 95-06, April 1995. DSI technical report, extended version of 1995-charme.pdf
  2. “Structure and Behaviour in Hardware Verification”
    K. G. W. Goossens.
    LFCS report 93-273, June 1993. An extended version of 1993-hol.pdf
  3. “The Formalisation of a Hardware Description Language in a Proof System: Motivation and Applications”
    K. G. W. Goossens.
    LFCS report 93-269, June 1993.
  4. “Operational Semantics Based Formal Symbolic Simulation”
    K. G. W. Goossens.
    LFCS report 92-231, September 1992.
  5. “Embedding a CHDDL in a Proof System”
    K. G. W. Goossens.
    LFCS report 91-155, May 1991.

Source:

http://www.es.ele.tue.nl/~kgoossens/research.html

http://compsoc.eu/

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