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Structure Type in SystemVerilog

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It has been there in VHDL all along, and now SystemVerilog has it too. In this article, you will learn what the new datatypes ‘structure’ and ‘union’ are and how they can help you in writing better and more legible code. It will also help you in answering the million dollar question (or, at least whatever dollar amount a license of your synthesis tool costs): are these constructs synthesizable?

Those Pesky Structure and Union Types

Article continues below…

A structure is a user-defined collection of various datatypes. Each of the constituent members of a structure is also called its field. These fields can be either standard datatypes (such as, int, time, logic, bit, to name a few) or, they can be user-defined types (using SystemVerilog typedef) and, possibly, another structure.

Essentially, a structure is a set of some inter-related data. Theoretically, the members of a structure can be defined separately and you can still work with all of them. But, wrapping them together in a structure helps you to organize these inter-related variables.

As an example below (note the keyword struct), in the structure floating_pt_num, both characteristic and mantissa are 32-bit value of type bit.

struct { 
   bit [31:0] characteristic; 
   bit [31:0] mantissa; 
} floating_pt_num;

Alternately, we could also write

typedef struct { 
   bit [31:0] characteristic; 
   bit [31:0] mantissa;
} flpt; 

flpt floating_pt_num;

Here, first we define a type flpt using typedef ad then use that to declare the variablefloating_pt_num.

Assigning a value to one or more fields of a structure is stright- forward.

floating_pt_num.characteristic = 32'h1234_5678;
floating_pt_num.mantissa       = 32'h0000_0010;

As mentioned, you can define a structure whose fields are other structures themselves.

typedef struct {
   flpt x; 
   flpt y; 
} coordinate;

The datatype union is very similar to a structure, but only one of the fields will be valid at a given point of time.

For instance, a variable point can be defined as the union shown below where only one of xy or r_theta is valid.

union {
   coordinate xy;
   coordinate r_theta;
} point;

Those of you who are already familiar with C style structure and union types, will no doubt find the SystemVerilog definitions for structure and union to be very similar to their counterparts in C. However, various other unique features of SystemVerilog data types can also be applied to structure and unions. For example, it is possible to ‘pack’ a structure in memory without gaps between its bit fields. This may be useful for fast access of data during simulation and possibly smaller footprint of your simulation binary.

To do this, you need to use the packed keyword in the definition of a structure.

typedef struct packed { 
   bit [31:0] characteristic;
   bit [31:0] mantissa; 
} flpt;

The beauty of packed structures is that one or more bits from such a structure can be can be selected as if it were a pcaked array. For instance, flpt[47:32] in the above declaration is same as c[15:0].

Structures and Unions in Your Design

Although structures and unions look similar, they serve two entirely different purposes.

The main purpose of structures is to help you organize and arrange a set of related variables. Consider this example where a module sender sends a PCI Express packet as its outputs. A PCI Express packet consists of 17 fields such as a 12 bit wide length, a 32-bit or 64-bit wide address, a data payload field, and so on. A traditional output port definition for this module will look as follows.

Sender module: Take 1

module sender ( 
   ...
   output bit [11:0] length,
   output bit [63:0] address,
   output bit [63:0] data_payload,
   ...
);

However, all fields of PCI Express can be organized into three broad categories: a header (which contains length, address and 13 other fields), and a data payload. It is easy to see yu can significantly reduce the number of ports by defining a structureheader as follows.

Sender module: Take 2

typedef struct header {
   bit [11:0] length;
   bit [63:0] address;
   ... 
}; 

module sender ( 
   ...
   output header h, 
   output bit [63:0] data_payload, 
   ... 
);

Since we are at it, we might as well consider defining another structure pcie_packetthat encapsulate it all.

Sender module: Take 3

typedef struct header { 
   bit [11:0] length; 
   bit [63:0] address;
   ... 
}; 

typedef struct pcie_packet {
   header h; 
   bit [63:0] data_payload;
}; 
module sender ( 
   ...
   output pcie_packet p,
   ... 
);

No prize for guessing which one of the above looks cleanest.

A union, on the other hand, can be used to or more forms of the same variable. To continue with our last example, recall that the address field in a PCI Express packet can be either 32-bit or 64-bit. However, in all of the previous structures, address has been declared as 64-bit wide assuming 32 of those bits will remain unused. There is no other way in traditional Verilog to handle this. With the introduction of union, however, you can re-define

header as shown below.

typedef struct header {
   bit [11:0] length; 
   union { 
      bit [31:0] address_32; 
      bit [31:0] address_64; 
   } 
}

Here, only one of address_32 and address_64 will remain valid at any given point of time.

Are They Synthesizable?

While support for SystemVerilog-specific types (including structure and union) in synthesizers have just started showing up at the time of writing this article (June, 2004), there are strong indications that they will be supported by a large number of vendors. Both structure and union are synthesizable semantically, as long as you obey certain rule in coding them (no variable part-select etc.). If your synthesis tool vendor does not support structure and union, let them know that you want it.

Postscript 06/30/2004: Steve Smith from Synopsys informed us that “…the SystemVerilog Structures are synthesizable by (Synopsys) Design Compiler (from version 2003.12).”

Source:

http://www.project-veripage.com/sv_structure.php

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