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Multicore Systems Laboratory

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Lectures and labs illustrate how to build a multicore computer system. Topics include parallelism, instruction-set architecture, memory hierarchy, and communication primitives. Using a field-programmable gate array (FPGA) board, programmed with a simple multicore processor and a minimal software environment, students develop Verilog and software to implement different hardware/software designs for caches, messages, shared memory, and coordination primitives. The labs culminate in a term project which students describe in a design paper and in-class presentation. Provides instruction in written and oral communication.

Lectures
  • L01: Multicore Intro [PDF]
  • L01: Beehive Overview [PDF]
  • L02: Computation Models [PDF]
  • L02 & L03: Intro to Verilog [PDFNewMessenger.v]
  • L04: Parallel Computing Patterns [PDF]
  • L05: Parallel TSP [PDF]
  • L06: Hardware Transactional Memory on Beehive [PDF]
  • L07: Shared Memory Architectures Programming and Synchronization [PDF]
  • L08: Shared Memory Programming and Wait-Free Synchronization [PDF]
  • L09: Shared Memory Software Coherence and Fences [PDF]
  • L10: Shared Memory Cache Coherence [PDF]
  • L11: Shared Memory Cache Coherence II [PDF]
  • L12: Final Projects, Quiz1 Review, Labs 3 and 4 [PDF]
  • L13: Shared Memory Cache Coherence III [PDF]
  • L14: Interconnection Networks [PDF]
  • L15: Scalable Synchronization [PDF]
  • L16: Interconnection Networks II [PDF]
  • L17: Interconnection Networks III [PDF]
  • L18: Case Study I: Tilera Multicore [PDF]
  • L19: Case Study II: AMD CC and Linux Scalability [PDF]
Labs

Beehive
Docs
  • Beehive: A many-core computer for FGPAs [PDF]
  • Apiary: Software Tools for Beehive [PDF]
  • libmc: a Multi-core Library for Beehive [PDF]
Other
Docs
  • Xilinx XUPV5 Board User Guide [PDF]
  • Verilog Reference Guide [PDF]

Source:

http://web.mit.edu/6.173/www/currentsemester/

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