About the Course
A modern VLSI chip is a remarkably complex beast: billions of transistors, millions of logic gates deployed for computation and control, big blocks of memory, embedded blocks of pre-designed functions designed by third parties (called “intellectual property” or IP blocks). How do people manage to design these complicated chips? Answer: a sequence of computer aided design (CAD) tools takes an abstract description of the chip, and refines it step-wise to a final design. This class focuses on the major design tools used in the creation of an Application Specific Integrated Circuit (ASIC) or System on Chip (SoC) design. Our focus is on the key representations that make it possible to synthesize, and to verify, these designs, as they move from logic to layout.
Our goal is for students to understand how the tools themselves work, at the level of their fundamental algorithms and data structures. You should be taking this course if (1) you are interested in building VLSI design tools; (2) you are interested in designing VLSI chips, and you want to know why the tools do what they do; (3) you just like cool algorithms, that work on big cool problems that involve bits, and gates, and geometry, and graphs, and matrices, and time, and…
About the Instructor(s)
Rob A. Rutenbar is the Abel Bliss Professor and Head of the Department of Computer Science at the University of Illinois at Urbana-Champaign. He received his PhD from the University of Michigan in 1984, and spent the next 25 years on the faculty at Carnegie Mellon University. He joined Illinois in 2010. He has worked on design tools for integrated circuits for the last 30 years, in areas ranging from synthesis, to optimization, to formal verification, simulation, and geometric layout. On a leave of absence from CMU in 1998, he cofounded Neolinear Inc. to commercialize the first successful tools for analog circuit design; he served as Neolinear’s Chief Scientist until its acquisition by Cadence (NASDAQ: CDNS) in 2004. His research spans both chip design methods (with recent focus on modeling the messy statistics of nanoscale silicon) and custom silicon chip architectures (for tough tasks like speech recognition, and machine learning).
Prof. Rutenbar has won many awards for his work. He is a Fellow of the IEEE and the ACM. He received the 2001 Semiconductor Research Corporation Aristotle Award in recognition of the impact of his teaching and his students on the US semiconductor industry. He received the 2007 IEEE CAS Industrial Pioneer Award for his contributions to making circuit synthesis tools a commercial success. Most recently, he won the 2011 IEEE Transactions on Computer-Aided Design Donald O. Pederson Best Paper Award for work on rare event failure statistics in nanoscale memory design.
Topics covered will include: Computational boolean algebra; logic verification; logic synthesis (2-level and multi-level); technology mapping; timing analysis; ASIC placement and routing.
Programming experience (C++, Java) and basic knowledge of data structures and algorithms. An understanding of basic digital design: Boolean algebra, Kmaps, gates and flip flops, finite state machine design. Linear algebra and calculus at the level of a junior or senior in engineering. Exposure to basic VLSI at an undergraduate level is nice — but it’s not necessary. We will keep the course self-contained, but students with some VLSI will be able to skip some background material.
The course is designed to be self-contained. However, we will offer pointers to original source material, i.e., papers in conferences and journals. This area lacks a single, established “front-to-back” text, that covers logic and layout, as well as representation, optimization, synthesis and verification. So, we will work to be as complete as possible in the lectures.
The class will consist of lecture videos, which are between 15 and 20 minutes in length. These contain 1-2 integrated quiz questions per video. There will also be standalone homeworks that are not part of video lectures, a few programming assignments, and a (not optional) final exam.