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CS/ECE 3700 – Digital System Design Spring 2012

brown2elarge

“If you’ve ever opened up your computer to get all the pizza crumbs out, you probably noticed that there’s nothing in there but a shiny green board covered with silver lines and lots of little black doodads. This class will attempt to teach you what those doodads are, how they work, and why it costs so much to fix when you spill stuff all over them.”
– Bill Richardson, Former 3700 TA 
A more formal definition of this class might be: 
The purpose of CS 3700 is to introduce you to the fundamental concepts of digital system theory and design. This includes techniques for defining and minimizing logic functions, design of combinational and sequential logic circuits, state diagrams, Mealy and Moore finite state machine models, design with MSI and LSI parts, design with Field Programmable Gate Arrays (FPGAs), and system controller design. By the end of the course you should be able to understand digital problem descriptions, design and optimize a solution, and build, test, and debug the resulting circuit.

Behind any engineering system is an efficient model that allows to analyze (and optimize) its characteristics. Digital circuits can be easily modeled using concepts such as Boolean algebra. Hence Boolean algebra is a fundamantal part of this course. This algebra allows to make Logical decisions, analyses and optimizations over a digital design so as to make it function correctly and robustly. This is something that you will learn in this course.

Secondly, this course is about designing systems. “Design” is really both a science and an art. The science is, of course, written in the books. But how to interpret that science and transform it into a functioning product is an art – something that you learn only by experience. Hence, this course will have a significant portion of design-work, both via HWs and Laboratory experiments. Finally, the course would be taught through a Computer-Aided Design (CAD) perspective.

Teaching staff

The instructor is Prof. Erik Brunvand.
Phone: 581-4345. Office: MEB 3142. Please use the teach-cs3700@list.eng.utah.edu mailing list to send email about the class.
Office Hours: Tuesday and Thursday after class, when my office door is open, or by appointment

Teaching assistants are TBA

Prerequisites

CS 1410 (Intro to CS) or 2000 (Intro to Programming), and PHYCS 2220: Physics for Scien. & Engineering II.

The purpose of the pre-reqs is to make sure that you have some basic programming background because we’ll be using the Verilog hardware description language. This is a programming language for describing hardware that looks (at least superficially) like C. So, I’m assuming that you have some basic programming background so we won’t have to go over basic programming concepts, and can jump right in to the specific features of Verilog.

The purpose of the Physics requirement is so that you will have seen basic electronics stuff: resistance, capacitance, current, voltage, Ohm’s law, Kirchoffs laws, etc.

College Administrative Guidelines

The College of Engineering Spring 2012 guidelines are here in PDF.

Textbook

Fundamentals of Digital Logic with Verilog Design, 2nd edition, by Stephen Brown and Zvonko Vranesic, c2008. Available at the University Bookstore and at various places on the web.

CAD Software

We’ll be using the free ISE WebPACK software from Xilinx for the labs. Important! Version 10.1 SP3 is required for this class because newer versions do not have support for our Spartan2 FPGAs. We’ll use this software for schematics, circuit and Verilog simulation, Verilog synthesis, and mapping circuits to the Xilinx FPGAs. You can download a free copy to your own PC at this Xilinx web site. You’ll have to register, but it doesn’t cost anything. If you want to install this on your own machine make sure that you scroll to the bottom and get version 10.1 SP3. Also be aware that our Xilinx boards require a parallel port for programming, so if you have a machine without a parallel port (which is most modern machines…) then you’ll be able to use the software for designing and simlulating your circuit, but you will have to come in to the lab to program the information onto your board.

Class Mailing Lists

There are two important class mailing lists:

  • cs3700@list.eng.utah.edu is a list of everyone in the class. I’ll use this list to send important information to everyone in the class!  This list has been populated with the email of all students who were preregistered for CS/ECE 3700. Note that this automatic processes used your <uid>@utah.edu email address, so please make sure that you’re reading that email address or have that address forward email to the place you do read your email. Also note that there is only one class mailing list even through there are two course numbers being used (CS3700 and ECE3700).
  • teach-cs3700@list.eng.utah.edu Email sent to this list will go to both the professor and the TAs. This is BY FAR the preferred method of asking questions! It lets all the teaching staff see and respond to the questions. Please use this email address unless you have very specific reasons for only sending email to one person.

Meeting times

  • Lectures: CS/EE 3700 lectures are on Tuesday and Thursday from 12:25-1:45 in WEB L101.
  • Labs: NOTE: Do not attend your lab in the first week of class. Labs will start in the second week of class.
    All labs will be held in the School of Computing Student Digital Systems Lab (DSL) which is MEB 3133.
  • NOTE We’ve made a few changes to the lab times.
  • Lab Session Changes are in red
  • Note that nobody is in Lab Session 3. If there are a few people who want to move, we’ll open it up. But we need at least 5-6 people who want to move to make that happen.
  • The roll sheets for each lab can be found here. Make sure you are listed in the lab that you want to be in!

  • Lab Session 2 TA: TBA Thursday 10:45a-12:05p
    Lab Session 3 TA: TBA Wednesday 10:20a-11:40a
    Lab Session 4 TA: TBA Wednesday 11:50a-1:10p
    Lab Session 5 TA: TBA Thursday 3:40p-5:00p
    Lab Session 6 TA: TBA Friday 1:25p-2:45p
    Lab Session 7 TA: TBA Friday 3:00p-4:20p

Office hours

Prof. Brunvand’s hours are after class, whenever his door is open, and by appointment in his office (3142 MEB).

The TAs hold their general office hours in the DSL. The times are:

  • Paymon: Monday 2:00-4:00
  • Leif: Tuesday 3:30-5:30

Grading policies


THERE IS NO PROVISION FOR TURNING IN LATE LABS OR ASSIGNMENTS


Grading will be based on the following:

  • Homework and Lab Assignments: 35%
  • Final Lab Project: 15%
  • MidTerm Exam I: 15%
  • MidTerm Exam II: 15%
  • Final Exam: 20%

Final point totals will be scaled so that the best student in the class has 100%. All students will be scaled by the that amount. Grade ranges will be:

  • Within 90% of the best student: Some sort of A
  • Within 80% of the best student: Some sort of B
  • Within 70% of the best student: Some sort of C
  • Within 55% of the best student: D
  • Below 50% scaled percentage: E

Cheating will not be tolerated! The School of Computing is adopting a “two strikes and you’re out” policy. This means:

  • The default penalty for cheating will be failure in the course. This counts as a strike.
  • In gray areas, an instructor may apply a less severe penalty. This does not count as a strike.
  • If you have two strikes, you will no longer be allowed to register for CS courses, or cross-listed courses taught by a CS professor.

A discussion of the cheating issue as it relates to this class can be found here

Official School of Computing policy on cheating: Given the unfortunate rise in cheatiing, the SoC faculty has decided to take a tougher stance in hopes of reversing things. In short – every instructor will define what they consider as cheating for each course. Starting now the default sanction for cheating is that the offender will be given a failing grade as the sanction. These sanctions will be recorded and kept in the SoC office in the student’s personal file. After the second such sanction, the offending student will be permanently dropped from any SoC degree program and if they are in another non-SoC program they will be subsequently prohibited from taking any more CS classes.

Part of the process is that every current undergraduate CS or CE major, or SoC graduate student must turn in a form acknowledging that they have read the policy and understand the penalties involved. Fortunately you only need to do this once during your degree program.

So you need to read the policy: http://www.cs.utah.edu/internal/cheating_policy.pdf

And print and sign this form: http://www.cs.utah.edu/internal/SoC_ack_form.pdf

For CE undergraduates, the form needs to be turned into Arlene Arenaz (MEB 3313)

For CS undergraduates, the form needs to be turned into Vicki Jackson (MEB 3190)

For SoC graduate students, the form needs to be turned into Ann Carlstrom (MEB 3190)


 

Assignments

Hand in hard-copy paper assignments in the box outside the School of Computing front office (MEB 3190). Make SURE to put your name and your lab section clearly on the front of the assignment. Partial credit is possible, but only if we can understand what you did, and how you reached that conclusion.

Lecture Plan

Here’s a link to an initial lecture schedule. Things will almost certainly drift a little, but here’s my plan at least. Please make SURE that you read the appropriate sections in the book BEFORE the lecture!

Handouts and Other Useful Information

Source:

http://www.eng.utah.edu/~cs3700/

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