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The demonstration implements a simple voice recorder. It is able to record the sound from the microphone, play it back at different speeds, and display the audio waveform on the VGA monitor.
You may download the Verilog source code for this demonstration here.
To get the presentation running, load the provided .sof file on the DE2 board. Connect the microphone to the MIC jack, and the speakers to the LINE-OUT jack. Connect the monitor to the VGA port on the DE2 board. If everything is setup properly, you should see something on the monitor, and the red LEDs on the DE2 board should be blinking.
You will most likely need to adjust the zoom level of the display to be able to see the waveforms. Refer to Table 1, “Voice recorder controls” for the instructions to do so. Once you have set the zoom level to a reasonable value, you should be able to see the waveforms generated by the ambient sounds. Please note that the zoom setting only affects the display, and not the recording, of the sounds.
|Play||Switch 0||Starts the playback. The playback starts from the beginning every time the switch is toggled.|
|Pause||Switch 1||Pauses the current operation. If the playback or recording was in progress, it is paused. The display is frozen. Led 8 blinks when pause is enabled.|
|Record||Switch 2||Starts recording. The recording always starts from the beginning of the memory. Any previous contents are overwritten. The recording will loop around once the memory capacity is exhausted.|
|Speed control||Switches 3 and 4||Adjusts the playback speed. The two switches represent the binary number which indicates the desired playback speed. When both switches are low, the sound is played at the original speed. Higher value means faster playback. The current playback speed is also displayed on the hex display #5.|
|Zoom control||Switches 5-8||Sets the display zoom level. Increase the value to zoom out, decrease to zoom in. There are 16 levels available. The current level is displayed on hex display #4, in hexadecimal.|
|Reset||Key 0||Resets the system. Note that the RAM is not cleared on reset.|
During the playback or recording, the relative elapsed time since the start of operation is displayed on the hex displays 6 and 7. The time is displayed in hexadecimal, and is proportional to the memory consumed so far. When the value reaches 0xff, the available memory is exhausted, and the operation starts over from the beginning.
The design performs three main functions: audio recording, audio playback and waveform display. At any given point, the circuit may be in the playback mode, recording mode, or neither. The waveform is always displayed, but the data source depends on the active mode.
In this mode, the audio is received from the microphone through the audio controller and stored in memory. Only the left channel data is stored. If the pause control is activated, the recording temporarily stops, and then resumes from the same point when the pause is deactivated.
If the memory is exhausted while in this mode, the address wraps around and starts overwriting the contents stored earlier.
While in this mode, the data source for the waveform display is the real-time microphone input.
In this mode, the audio data is loaded from the memory and sent to the speakers through the audio controller. Because only one channel of data is stored in memory, the contents are duplicated for the stereo playback. The pause control in this mode works as expected: once activated, the playback will temporarily stop, and then resume where it left off after pause is deactivated.
The audio is looped around indefinitely while in this mode. Once the memory is exhausted, the playback starts over from the beginning.
In this mode, the data source for the waveform display is the value being played from memory.
The waveform is displayed independently of the current mode. The data source for the waveforms changes as described above. When the circuit is idle (i.e., neither in the playback nor recording modes), the data is taken from the microphone input, same as in the audio recording mode.
The waveform display is frozen any time the pause is activated, and resumes once the pause is deactivated.
The zoom level controls the amplitude scaling of the wave that is displayed. The data values are essentially divided by the value derived from the zoom level before being drawn on screen. Thus the higher zoom level means the higher visible range, but also the loss of the weak signals.
The design consists of three main modules: the top-level module (in the file
vr.v), the audio playback and recording module (in the file
playrec.v), and the display module (in the file
display.v). Additionally, the design uses a number of third-party components. The SDRAM controller is used to access the SDRAM memory chip on the DE2 board, the VGA adapter is used to display the waveforms, and the audio controlleris used for the audio I/O. The system layout is illustrated in Figure 1, “System layout”.
The main purpose of this module is to connect all the sub-modules appropriately. In addition to this, it implements the control for the pause indicator and the zoom level.
The pause indicator is simply an LED which blinks when the pause switch is on. This is implemented by connecting the LED to the most significant bit of the delay counter.
The variable zoom is implemented by dividing the data values by the power of two corresponding to the current zoom level. In binary arithmetic, this operation is essentially a shift to the right by the given number of positions. However, because the data values are signed 2’s-complement integers, the result must be sign extended. Since Verilog does not provide a direct way to express this operation, the values were enumerated in a case statement (in the file
vr.v, line 74).
The playback and recording module controls the data flow between the audio controller and the SDRAM memory. The module consists of a state machine and the address counter, plus a few control signals.
The address counter is connected directly to the address lines of the memory controller and keeps track of the current memory position. The counter is controlled by the state machine, and can be incremented or reset. The playback speed control is connected directly to the counter and controls by how much the counter is incremented every cycle. A value greater than one causes the samples stored in memory to be skipped, and the playback becomes faster.
The state machine controls the interaction between memory and the audio controller. The user controls are given as the inputs to the state machine, and are used to select the operating mode. The state machine can be in three main modes: recording, playback, and idle. The simplified state diagram is shown in Figure 2, “State diagram for the playback/recording FSM”. The Verilog implementation can be found in the file
playrec.v, starting on line 31.
In the recording mode, the state machine waits for the audio data (from the audio controller) to become available, increments the current memory address, and asserts the memory write signal. The data output from the audio controller is connected directly to the data input of the memory controller. After the memory write completes, the state machine transitions to the input check state, and if the inputs still indicate the recording mode, the cycle repeats.
In the playback mode, the state machine waits for the free space in the data buffers of the audio controller and then issues the memory read request. The data out lines of the memory controller are connected directly to the data in lines of the audio controller. After the memory read operation is completed, the audio write signal is asserted and the memory address is incremented. After this, the state machine proceeds to check the user inputs, and if the inputs indicate the playback mode, the cycle repeats.
The state machine will enter the idle mode either when the pause control is activated, or when neither the playback nor recording controls are activated. The only difference is that when pause is activated, the address counter is not reset. In this mode, the state machine just waits for the state change, and the address counter is disabled.
This module is responsible for plotting the provided data on the screen. The module consists of a simple state machine and a set of counters: one for X position, one for Y position, and one for delay. The data is plotted by sweeping the X and Y counters through the display range and setting the color appropriately. The sweep delay counter controls the delay between the X counter steps.
The state machine consists of only two states: one to indicate that the vertical sweep is in progress, and another to indicate that the vertical sweep is done. When the vertical sweep is done, the state machine waits for the sweep delay counter to reach the preset value, and, unless the display is to be frozen as indicated by the user input, proceeds to do another vertical sweep. The state machine is illustrated in Figure 3, “State diagram for the display FSM”. The Verilog implementation can be found in the file
display.v, line 19.
The Y counter runs when the state machine is in the vertical sweep state, and resets once the sweep is done. The counter value feeds the Y position input of the VGA adapter.
The X counter is incremented every time the vertical sweep is completed and the delay value (on the delay counter) is reached. The X counter feeds the X position input of the VGA adapter.
The current pixel (the one at the position given by the X and Y counters) color value is selected between the background and foreground color by comparing the value of the Y counter to the data input.
The design contains a number of small helper modules which will be shortly described in this section.
The hex2seg module is used to convert the four bit input value to the seven bit output suitable for HEX display control. The value represents a single hexadecimal digit.
The PLL module is used to implement the clock control. The design requires three additional clock signals to be generated: 25MHz for the VGA adapter, 12.5MHz for the audio chip, and 50MHz phase-delayed clock for the SDRAM chip. These clock signals are generated using the PLL module on the FPGA.
The SDRAM module provides the interface to the SDRAM chip on the DE2 board. The module abstracts the SDRAM control protocol such that the chip might be accessed as a linear memory with a 16-bit word size. The details of the operation of this module are beyond the scope of this document.
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