‎"Behind every stack of books there is a flood of knowledge."

VLSI Principles (UCSB)

ECE 124A

– ECE 124A – Very-Large-Scale Integration Principles
UCSB, ECE, Fall 2012

– Instructor: Prof. Kaustav Banerjee 
 kaustav (at)
Office: Harold Frank Hall (HFH) 4151
Phone: (805) 893-3337
Fax: (805) 893-3262

– Teaching Assistant: Jiahao Kang 
  jiahao_kang (at)
Office: HFH 2152C

– Lecture Location : ESB 1003
– Lecture Time: Tue. & Thu. 3:30-4:45PM

– Lab Location: HFH 1140 (Map )
– Lab Time: Tue. 8:00PM-10:50PM

– TA Office Hour Location:  HFH 1140
– TA Office Hour Time:  8:00PM-10:50PM

– More course info
– Syllabus

– Midterm : Nov. 9, 4-6 pm, ESB 1003
– Final Exam Date: Dec 13, 4-7 pm

4th Edition

Lecture 01 (09/27/2012) – Introduction
G. E. Moore, “Cramming more components onto integrated circuits,” Electronics Magazine, pp. 114-117, 1965. 
Lecture 02 (10/02/2012) – History of IC
Intel, “From Sand to Circuit” and  Intel, “From Sand to Silicon” 
Lecture 03 (10/04/2012) – CMOS Implements and Video: Silicon Run
Lecture 04 (10/09/2012) – CMOS Process and Video: Silicon Run
K. Banerjee, “3-D ICs: A Novel Chip Design for Improving Deep-Submicrometer Interconnect Performance and Systems-on-Chip Integration”, Proceedings of the IEEE, 2001 
Lecture 05 (10/16/2012) – Layout, Stick diagram and Eular path
Lecture 06 (10/16/2012) – Semiconductor Physics
Lecture 07 (10/23/2012) – Device Physics (P-N Junction and MOS Capacitor)
Lecture 08 (10/25/2012) – MOSFET
Lecture 09 (10/30/2012) – MOSFET and Inverter
Lecture 10 (11/01/2012) – Inverter
Lecture 11 (11/06/2012) – Inverter Sizing
S. Borkar, “Design Challenges of Technology Scaling,” IEEE Micro, pp. 23-29, 1999.
Lecture 12 (11/08/2012) – Interconnect
K. Banerjee, “A Power-Optimal Repeater Insertion Methodology for Global Interconnects in Nanometer Designs”, IEEE TED, 2002;
K. Banerjee, “Analysis of On-Chip Inductance Effects for Distributed RLC Interconnects”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2002.
Lecture 13 (11/13/2012) – Combinational Logic Circuits
Lecture 14 (11/15/2012) – Ratioed Logic, Dynamic CMOS
H.F. Dadgour, et al., “A New Paradigm in the Design of Energy-Efficient Digital Circuits Using Laterally-Actuated Double-Gate NEMS”, IEEE ISLPED, 2010;
H. F. Dadgour, et al , “A Novel Variation-Tolerant Keeper Architecture for High-Performance Low-Power Wide Fan-in Dynamic Gates”, IEEE TVLSI, 2010.
Lecture 15 (11/27/2012) – Sequential Logic Circuits
Lecture 16 (11/29/2012) – Memory
Lecture 17 (12/04/2012) – Datapath

Homework 1 (Due 10/05/2012 Fri) – Review of Digital Design
Homework 2 (Due 10/15/2012 Mon) – CMOS implements and Pass Transistors
Reference:  A general meth od in synthesis of pass-transistor circuits
Homework 3 (Due 10/29/2012 Mon) – Semiconductor Device Physics
Homework 4 (Due 11/07/2012 Wed) – MOSFET Physics
Threshold voltage definition and extraction for deep-submicron MOSFETs 
Homework 5 (Due 11/21/2012 Wed) – Inverter, CMOS Sizing, Interconnect
Homework 6 (Due 12/07/2012 Fri) – Pass Transistors, Dynamic CMOS, Sequential Logic, Memory and Datapath

– Do NOT – Do not copy from each other!
– Homework Box is at HFH 3120

– For environment setup guidence, see Lab 1 .
– HSpice MOS Model Libraries:

Lab 1 (Due 10/08/2012 Mon) – Environment setup and tool practice
Related files:.bashrcinv.sp and 180nm_bulk.txt
Lab 2 (Due 10/17/2012 Wed) – HSpice practice, CMOS sizing
Lab 3 (Due 10/26/2012 Fri) – Single-stage CMOS logic gate layout
(a practice for Eular path and stick diagrams)
Lab 4 (Due 11/21/2012 Wed) – Inverter VTC; CMOS Sizing and Delay layout

– Lab reports should be handed in to homework box.
– You will need to use these software: (Manuals provided)

– HSpice (Circuit Netlist Simulation) – HSpice Manual
– CosmosScope/AvanWaves
(Waveform viewer for Linux/Windows)
– CScope Manual 
– AvanWaves Manual
– MAX (Circuit Layout Editor) – MAX Tutorial v3.2
– SUE (Schematic Capture Program) – SUE Tutorial v4.1   v5.0.7

– Warning: Please do NOT print copies of these manuals!

– Final Project

– Project Reference:
LVS Technology for the Intel(R) Pentium(R) 4 Processor on 90nm Technology

– Work either individually or in a group of maximum two.
Group list (Please sign up)

Final project timeline Notes:
– 11/23/2012 Fri Hand in a report for Part 1/4 (reference review) .
– 11/28/2012 Wed Hand in a report for Part 2/4 (DCN and CDL cells).
– 12/05/2012 Wed Hand in a report for Part 3/4 (SA and bitslide cells).
– Final week
Interview for Part 4/4 (16-bit adder):
Each student in a group will be orally examined by the TA.
Cancelled – will be integrated in Final Exam
– 12/17/2012 Mon Hand in a complete report for the whole project.

– Midterm 2011  Solutions

– Midterm 2012  Solutions



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This entry was posted on January 9, 2013 by in Courses, Electronic & Computer Engineering, IC Design & Fabrication, Science & Technology.
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